Datasheet > W83194R-67B

W83194R-67B

更新时间： 2024-02-10 18:21:03

品牌	Logo	应用领域
华邦 - WINBOND		时钟
页数	文件大小	规格书
18页	257K
描述
100MHZ 3-DIMM CLOCK FOR VIA MVP4

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W83194R-67B 技术参数

生命周期：	Obsolete	零件包装代码：	SSOP
包装说明：	SSOP, SSOP48,.4	针数：	48
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.23
其他特性：	ALSO REQUIRES 2.5V SUPPLY	JESD-30 代码：	R-PDSO-G48
JESD-609代码：	e3	长度：	15.875 mm
端子数量：	48	最高工作温度：	70 °C
最低工作温度：		最大输出时钟频率：	133 MHz
封装主体材料：	PLASTIC/EPOXY	封装代码：	SSOP
封装等效代码：	SSOP48,.4	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, SHRINK PITCH	电源：	2.5,3.3 V
主时钟/晶体标称频率：	14.318 MHz	认证状态：	Not Qualified
座面最大高度：	2.794 mm	子类别：	Clock Generators
最大供电电压：	3.465 V	最小供电电压：	3.135 V
标称供电电压：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	MATTE TIN	端子形式：	GULL WING
端子节距：	0.635 mm	端子位置：	DUAL
宽度：	7.5 mm	uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, PROCESSOR SPECIFIC

W83194R-67B 数据手册

W83194R-67B

PRELIMINARY

8.0 FUNCTION DESCRIPTION

8.1 POWER MANAGEMENT FUNCTIONS

All clocks can be individually enabled or disabled via the 2-wire control interface. On power up,

external circuitry should allow 3 ms for the VCO? to stabilize prior to enabling clock outputs to assure

correct pulse widths. When MODE=0, pins 15 and 46 are inputs (PCI_STOP#), (CPU_STOP#), when

MODE=1, these functions are not available. A particular clock could be enabled as both the 2-wire

serial control interface and one of these pins indicate that it should be enable.

The W83194R-67B may be disabled in the low state according to the following table in order to

reduce power consumption. All clocks are stopped in the low state, but maintain a valid high period

on transitions from running to stop. The CPU and PCI clocks transform between running and stop by

waiting for one positive edge on PCICLK_F followed by negative edge on the clock of interest, after

which high levels of the output are either enabled or disabled.

CPU_STOP#

PCI_STOP#

CPUCLK 0:2,

SDRAM 0:11

PCI

SDRAM_F,

OTHER CLKs

CPU_F,PCI_F

LOW

RUNNING

LOW

RUNNING

8.2 2-WIRE I²C CONTROL INTERFACE

The clock generator is a slave I²C component which can be read back? The data stored in the

latches for verification. All proceeding bytes must be sent to change one of the control bytes. The 2-

wire control interface allows each clock output individually enabled or disabled. On power up, the

W83194R-67B initializes with default register settings, and then it is optional to use the 2-wire control

interface.

The SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK is high

during normal data transfer. There are only two exceptions. One is a high-to-low transition on

SDATA while SDCLK is high used to indicate the beginning of a data transfer cycle. The other is a

low-to-high transition on SDATA while SDCLK is high used to indicate the end of a data transfer

cycle. Data is always sent as complete 8-bit bytes followed by an acknowledge generated.

Byte writing starts with a start condition followed by 7-bit slave address and a write command bit

[1101 0010], command code checking [0000 0000], and byte count checking. After successful

reception of each byte, an acknowledge (low) on the SDATA wire will be generated by the clock chip.

Controller can start to write to internal I²C registers after the string of data. The sequence order is as

follows:

Publication Release Date: Dec.. 1999

- 6 -

Revision 0.50

1...3 4 567 8 9...18

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W83194R-WE	ETC	CPU SYSTEM CLOCK GENERATOR\|CMOS\|SSOP\|48PIN\|PLASTIC	获取价格
W83195AR-25	WINBOND	200MHZ 3-DIMM CLOCK FOR SOLANO CHIPSET	获取价格
W83195AR-WE	WINBOND	200MHZ 3-DIMM CLOCK FOR WHITNEY CHIPSET	获取价格
W83195BG-101	WINBOND	Winbond Clock Generator For Intel 915/925 Chipsets	获取价格

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