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W83195BR-25 PDF预览

W83195BR-25

更新时间: 2024-01-03 13:59:40
品牌 Logo 应用领域
华邦 - WINBOND 晶体时钟发生器微控制器和处理器外围集成电路光电二极管电脑PC个人电脑
页数 文件大小 规格书
18页 260K
描述
个人PC频率控制IC

W83195BR-25 技术参数

生命周期:Transferred零件包装代码:SSOP
包装说明:SSOP, SSOP56,.4针数:56
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.44
其他特性:ALSO REQUIRES 2.5V SUPPLYJESD-30 代码:R-PDSO-G56
JESD-609代码:e3长度:18.415 mm
端子数量:56最高工作温度:70 °C
最低工作温度:最大输出时钟频率:153.33 MHz
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装等效代码:SSOP56,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH电源:2.5,3.3 V
主时钟/晶体标称频率:14.318 MHz认证状态:Not Qualified
座面最大高度:2.794 mm子类别:Clock Generators
最大压摆率:100 mA最大供电电压:3.465 V
最小供电电压:3.135 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:MATTE TIN
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL宽度:7.5 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFICBase Number Matches:1

W83195BR-25 数据手册

 浏览型号W83195BR-25的Datasheet PDF文件第2页浏览型号W83195BR-25的Datasheet PDF文件第3页浏览型号W83195BR-25的Datasheet PDF文件第4页浏览型号W83195BR-25的Datasheet PDF文件第5页浏览型号W83195BR-25的Datasheet PDF文件第6页浏览型号W83195BR-25的Datasheet PDF文件第7页 
W83195BR-25  
200MHZ 3-DIMM CLOCK FOR SOLANO CHIPSET  
1.0 GENERAL DESCRIPTION  
The W83195BR-25 is a Clock Synthesizer for Intel 815 Solano chipset. W83195BR-25 provides all  
clocks required for high-speed RISC or CISC microprocessor and also provides 64 different  
frequencies of CPU, SDRAM, PCI, 3V66, IOAPIC clocks frequency setting. All clocks are externally  
selectable with smooth transitions.  
The W83195BR-25 provides I2C serial bus interface to program the registers to enable or disable  
each clock outputs and provides 0.25% and 0.5% center type spread spectrum to reduce EMI.  
The W83195BR-25 provides stepless frequency programming by controlling the VCO freq. and the  
clock output divisor ratio. Also skew of CPU,SDRAM and 3V66 clock outputs are programmable. A  
watch dog timer is quipped and when time out, the RESET# pin will output 4ms pulse signal.  
The W83195BR-25 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.  
High drive PCI and SDRAM CLOCK outputs typically provide greater than 1 V /ns slew rate into 30  
pF loads. CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads as  
maintaining 50± 5% duty cycle. The fixed frequency outputs as REF, 24MHz, and 48 MHz provide  
better than 0.5V /ns slew rate.  
2.0 PRODUCT FEATURES  
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2 CPU clocks (2.5V)  
3 3V-66 clocks (3.3V)  
12 SDRAM clocks for 3 DIMMs(3.3V)  
8 PCI synchronous clocks.  
Optional single or mixed supply:  
(VDDR = VDDP=VDDS = VDD48 = VDD3 = 3.3V, VDDA=VDDC=2.5V)  
Skew form CPU to PCI clock -1 to 4 ns, center 2.6 ns  
Smooth frequency switch with selections from 66.8 to 200MHz  
I2C 2-Wire serial interface and I2C read back  
0.25% center and 0.5% center type spread spectrum  
Programmable registers to enable/stop each output and select modes  
(mode as Tri-state or Normal )  
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·
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48 MHz for USB  
24 MHz for super I/O  
·
Packaged in 56-pin SSOP  
Publication Release Date: May 2000  
Revision 0.52  
- 1 -  

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