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W83194R-630A PDF预览

W83194R-630A

更新时间: 2024-11-19 22:14:35
品牌 Logo 应用领域
华邦 - WINBOND 时钟
页数 文件大小 规格书
11页 159K
描述
166MHZ CLOCK FOR SIS CHIPSET

W83194R-630A 数据手册

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W83194R-630A  
166MHZ CLOCK FOR SIS CHIPSET  
1. GENERAL DESCRIPTION  
The W83194R-630A is a Clock Synthesizer for SiS 540/630 chipset. W83194R-630A provides all  
clocks required for high-speed RISC or CISC microprocessor such as AMD,Cyrix,Intel Pentium,  
Pentium II and also provides 16 different frequencies of CPU clocks frequency setting. All clocks are  
externally selectable with smooth transitions. The W83194R-630A makes SDRAM in synchronous or  
asynchronous frequency with CPU clocks.  
The W83194R-630A provides I2C serial bus interface to program the registers to enable or disable  
each clock outputs and W83194R-630A provides the 0.5%, 0.75% center type and 0~0.5% down type  
spread spectrum to reduce EMI.  
The W83194R-630A accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.  
High drive PCI and SDRAM CLOCK outputs typically provide greater than 1 V /ns slew rate into 30  
pF loads. CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads as  
maintaining 50± 5% duty cycle. The fixed frequency outputs as REF, 24MHz, and 48 MHz provide  
better than 0.5V /ns slew rate.  
2. PRODUCT FEATURES  
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Supports PentiumÔ , PentiumÔ II, AMD and Cyrix CPUs with I2C.  
3 CPU clocks  
14 SDRAM clocks for 3 DIMMs  
7 PCI synchronous clocks.  
Optional single or mixed supply:  
(All Vdd = 3.3V) or (Other s Vdd = 3.3V, VddLCPU=2.5V)  
Skew form CPU to PCI clock 1 to 4 ns, center 2.6 ns  
SDRAM frequency synchronous or asynchronous to CPU clocks  
Smooth frequency switch with selections from 66 to 166mhz  
I2C 2-Wire serial interface and I2C read back  
0.5%, 0.75%center type, 0~0.5% down type spread spectrum to reduce EMI  
Programmable registers to enable/stop each output and select modes  
(mode as Tri-state or Normal )  
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48 MHz for USB  
24 MHz for super I/O  
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Packaged in 48-pin SSOP  
Publication Release Date: Nov. 1999  
Revision 0.65  
- 1 -  

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