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W83194R-67A PDF预览

W83194R-67A

更新时间: 2024-11-19 22:25:27
品牌 Logo 应用领域
华邦 - WINBOND 时钟
页数 文件大小 规格书
18页 234K
描述
100MHZ 3-DIMM CLOCK FOR VIA MVP4

W83194R-67A 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SSOP包装说明:SSOP-48
针数:48Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.31其他特性:ALSO REQUIRES 2.5V SUPPLY
JESD-30 代码:R-PDSO-G48JESD-609代码:e0
长度:15.875 mm端子数量:48
最高工作温度:70 °C最低工作温度:
最大输出时钟频率:124 MHz封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装等效代码:SSOP48,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度):NOT SPECIFIED电源:2.5,3.3 V
主时钟/晶体标称频率:14.318 MHz认证状态:Not Qualified
座面最大高度:2.794 mm子类别:Clock Generators
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.5 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFICBase Number Matches:1

W83194R-67A 数据手册

 浏览型号W83194R-67A的Datasheet PDF文件第2页浏览型号W83194R-67A的Datasheet PDF文件第3页浏览型号W83194R-67A的Datasheet PDF文件第4页浏览型号W83194R-67A的Datasheet PDF文件第5页浏览型号W83194R-67A的Datasheet PDF文件第6页浏览型号W83194R-67A的Datasheet PDF文件第7页 
W83194R-67A  
100MHZ 3-DIMM CLOCK FOR VIA MVP4  
1.0 GENERAL DESCRIPTION  
The W83194R-67A is a Clock Synthesizer which provides all clocks required for high-speed RISC or  
CISC microprocessor such as Intel Pentium , AMD and Cyrix. W83194R-67A provides sixteen  
CPU/PCI frequencies which are externally selectable with smooth transitions. W83194R-67AA also  
provides 13 SDRAM clocks controlled by the none-delay buffer_in pin.  
The W83194R-67A accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.  
¡ Ó  
¡ Ó  
Spread spectrum built in at 0.5% or 0.25% to reduce EMI. Programmable stopping individual  
clock outputs and frequency selection through I2C interface. The device meets the Pentium power-up  
stabilization, which requires CPU and PCI clocks be stable within 2 ms after power-up.  
High drive six PCI and thirteen SDRAM CLOCK outputs typically provide greater than 1 V /ns slew  
rate into 30 pF loads. Two CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20  
¡ Ó  
pF loads as maintaining 50 5% duty cycle. The fixed frequency outputs as REF, 24MHz, and 48  
MHz provide better than 0.5V /ns slew rate.  
2.0 PRODUCT FEATURES  
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Supports PentiumÔ , AMD, Cyrix CPU with I2C.  
4 CPU clocks (one free-running CPU clock)  
13 SDRAM clocks for 3 DIMs  
6 PCI synchronous clocks  
Optional single or mixed supply:  
(Vddq1=Vddq2 = Vddq3 = Vddq4 = VddL1 =VddL2= 3.3V) or (Vddq1= Vddq2 = Vddq3=Vddq4 =  
3.3V, VddL1 = VdqL2 = 2.5V)  
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< 250ps skew among CPU and SDRAM clocks  
< 4ns propagation delay SDRAM from buffer input  
Skew from CPU(earlier) to PCI clock -1 to 4ns, center 2.6ns.  
Smooth frequency switch with selections from 60 MHz to 124 MHz CPU  
I2C 2-Wire serial interface and I2C read back  
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0.25% or 0.5% spread spectrum function to reduce EMI  
Programmable registers to enable/stop each output and select modes  
(mode as Tri-state or Normal )  
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2ms power up clock stable time  
MODE pin for power Management  
One 48 MHz for USB & one 24 MHz for super I/O  
48-pin SSOP package  
Publication Release Date: Feb. 1999  
Revision 0.30  
- 1 -  

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