FULL SIZE D.I.L.
M package
M2911 thru M2913
VOLTAGE CONTROLLED
CRYSTAL OSCILLATORS
DOUBLE WIDE D.I.L.
W package
W2911 thru W2913
W2971 thru W2973
ECLPS 5V PECL with Extremely Low Jitter
Complementary Output
Thru-Hole
Description
Commercial: 0º to 70ºC
15 MHz to 175 MHz
These ECLPS VCXOs feature super-low
jitter of 20 ps peak-to-peak — within the
bandwidth of 12 KHz to 20 MHz the jitter
will not exceed 1 ps RMS. They are
based on the same logic as our M2910s
fixed frequency oscillators, and therefore
exhibit identical waveform characteristics.
These thru-hole VCXOs are designed for
compatibility with digital and communica-
tions systems based on the ECLPS
These VCXOs provide complementary PECL outputs thru 175 MHz
with extremely fast rise and fall times. Each oscillator is computer
tuned and computer tested to guarantee stability and frequency
pull at 0º, 25º and 70ºC. All oscillators will capture the rated pull
at all operating temperatures.
FEATURES
family of high speed PECL logic.
• Jitter less than 1 ps RMS from 12 KHz to 20 MHz
• Super low jitter of 20 ps peak to peak maximum limits loss of data packets in digital data recovery
• Will drive standard interface chips in complementary PECL.
• Duty Cycle is typically 48/52
Users have a choice of the three most
widely used combinations of pull, control
voltage and center frequency deviation.
The oscillators are available at frequencies
from 15 to 175 MHz. Standard frequency
stability is ±20 ppm.
• Three frequency deviation choices
• Output is PECL with typical rise and fall times of 225 ps
• Exceptional linearity with Deviation Sensitivity Ratio not exceeding 2.0
• Package is choice of double DIL, standard DIL with 7 pins (M1)
All models have dual complementary
outputs. All feature 250 ps typical rise/fall
times and provide superior jitter. Their low
output impedance and dual complemen-
tary outputs preserve waveform symmetry
when sending the timing waveforms over
appreciable distance. Output symmetry of
45/55 is standard.
TYPICAL APPLICATIONS
• Used in Sonet ST33 interface for generation of the transmitter data clock
SPECIAL APPLICATION NOTES
All outputs must be loaded with 270 ohms to ground, or 50 ohms to +3V
•
Outputs will drive all PECL families when they are operated in PECL configurations
•
0.98 max
(24.89)
Designed originally for advanced SONET
applications, their combination of advanced
characteristics provides special appeal to
designers of highly evolved phase-locked-
loop circuits. They provide tight control of
the voltage-to-frequency (∆F/∆V) transfer
function and feature jitter specifications of
less than 20 pico-seconds peak-to-peak.
Typical RMS jitter is 2.048 ps RMS.
0.80 max
(20.32)
DOT
DENOTES
PIN 1
Square corner indicates Pin
1
0.275 max
(6.99)
.20 MAX
.20 MIN.
.100 typ
0.20/0.30
(.50/.76)
(.025)
0.700 ±.005
(17.78 ±.13)
.018 – .001
100 TYP (NON
ACCUMULATIVE)
0.20.24
(0.51/.61
Pin 1
Centrally Located
These VCXOs are hermetically sealed in
full size (H) or wide (W) DIL packages.
Models W2911 through W2913 accept
control voltage input on pin 1, while
Models W2971 through W2973 accept
control voltage on pin 6. All models are
tested and guaranteed over full 0°C to
70°C temperature.
Pin 1
.016/.019 Dia
(.41/.48), 16 pins
2
5
7
8
.300 – .005
8
.500 – .005
150
0.600 ±.005
Centrally Located
14
9
9
16
.300
– .005
44 MAX
Glass Insulators (3)
.800 – .005
“M-1” Package
“W1” Package
ELECTRONICS
10 Commerce Dr
• New Rochelle NY 10801
+
International Sales: 1.914-712-2200 • USA Sales: +1.800.331.1236 • Fax: 914.712.2290 • www.mfelectronics.com • email:sales@mfelectronics.com
1 of 3
5秒后页面跳转
解析光耦仿真器：升级光耦合器技术的必要性
英伟达新一代Blackwell GPU过热问题致交付延迟
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
