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W29C011AP15N PDF预览

W29C011AP15N

更新时间: 2024-11-08 21:11:27
品牌 Logo 应用领域
华邦 - WINBOND 可编程只读存储器内存集成电路
页数 文件大小 规格书
19页 166K
描述
128KX8 FLASH 5V PROM, 150ns, PQCC32, PLASTIC, LCC-32

W29C011AP15N 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFJ
包装说明:QCCJ, LDCC32,.5X.6针数:32
Reach Compliance Code:compliant风险等级:5.71
最长访问时间:150 ns命令用户界面:NO
数据轮询:YESJESD-30 代码:R-PQCC-J32
JESD-609代码:e0长度:13.97 mm
内存密度:1048576 bit内存集成电路类型:FLASH
内存宽度:8功能数量:1
端子数量:32字数:131072 words
字数代码:128000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:128KX8封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC32,.5X.6
封装形状:RECTANGULAR封装形式:CHIP CARRIER
页面大小:128 words并行/串行:PARALLEL
峰值回流温度(摄氏度):225电源:5 V
编程电压:5 V认证状态:Not Qualified
座面最大高度:3.56 mm最大待机电流:0.0001 A
子类别:Flash Memories最大压摆率:0.05 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30切换位:YES
类型:NOR TYPE宽度:11.43 mm
最长写入周期时间 (tWC):10 msBase Number Matches:1

W29C011AP15N 数据手册

 浏览型号W29C011AP15N的Datasheet PDF文件第2页浏览型号W29C011AP15N的Datasheet PDF文件第3页浏览型号W29C011AP15N的Datasheet PDF文件第4页浏览型号W29C011AP15N的Datasheet PDF文件第5页浏览型号W29C011AP15N的Datasheet PDF文件第6页浏览型号W29C011AP15N的Datasheet PDF文件第7页 
W29C011A  
´ 8 CMOS FLASH MEMORY  
128K  
GENERAL DESCRIPTION  
The W29C011A is a 1-megabit, 5-volt only CMOS flash memory organized as 128K ´ 8 bits. The  
device can be programmed and erased in-system with a standard 5V power supply. A 12-volt VPP is  
not required. The unique cell architecture of the W29C011A results in fast program/erase operations  
with extremely low current consumption (compared to other comparable 5-volt flash memory products).  
The device can also be programmed and erased using standard EPROM programmers.  
FEATURES  
· Single 5-volt program and erase operations  
· Fast page-write operations  
· Low power consumption  
- Active current: 25 mA (typ.)  
- Standby current: 20 mA (typ.)  
- 128 bytes per page  
- Page program cycle: 10 mS (max.)  
- Effective byte-program cycle time: 39 mS  
- Software-protected data write  
· Fast chip-erase operation: 50 mS  
· Read access time: 150 nS  
· Automatic program timing with internal VPP  
generation  
· End of program detection  
- Toggle bit  
- Data polling  
· Latched address and data  
· TTL compatible I/O  
· JEDEC standard byte-wide pinouts  
· Page program/erase cycles: 1,000  
· Ten-year data retention  
· Software and hardware data protection  
· Available packages: 32-pin 600 mil DIP, 450 mil  
SOP and PLCC  
Publication Release Date: January 31, 2002  
- 1 -  
Revision A3  

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