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W19B320ABT8G PDF预览

W19B320ABT8G

更新时间: 2023-01-03 01:47:46
品牌 Logo 应用领域
华邦 - WINBOND 光电二极管
页数 文件大小 规格书
53页 479K
描述
Flash, 2MX16, 70ns, PDSO48, 12 X 20 MM, TSOP-48

W19B320ABT8G 数据手册

 浏览型号W19B320ABT8G的Datasheet PDF文件第6页浏览型号W19B320ABT8G的Datasheet PDF文件第7页浏览型号W19B320ABT8G的Datasheet PDF文件第8页浏览型号W19B320ABT8G的Datasheet PDF文件第10页浏览型号W19B320ABT8G的Datasheet PDF文件第11页浏览型号W19B320ABT8G的Datasheet PDF文件第12页 
W19B320AT/B  
6.1.7 #RESET: Hardware Reset Pin  
The #RESET pin provides a hardware method to reset the device to reading array data. When the  
#RESET pin is set to low for at least a period of tRP, the device will immediately terminate every  
operation in progress, tri-states all output pins, and ignores all read/write commands for the duration  
of the #RESET pulse. The device also resets the internal state machine to reading array data mode.  
To ensure data integrity, the interrupted operation needs to be reinitiated when the device is ready to  
accept another command sequence.  
Current is reduced for the duration of the #RESET pulse. When #RESET is held at VSS ± 0.3V, the  
device initiates the CMOS standby current (ICC4). If #RESET is held at VIL but not within VSS ± 0.3V,  
the standby current will be greater.  
The #RESET pin may be tied to the system-reset circuitry. Thus the system reset would also reset the  
device, enabling the system to read the boot-up firmware from the device.  
If #RESET is asserted during the program or erase operation, the RY/#BY pin will be at “0” (busy) until  
the internal reset operation is complete. If #RESET is asserted when a program or erase operation is  
not processing (RY/#BY pin is “1”), the reset operation is completed within a time of tREADY (not during  
Embedded Algorithms). After the #RESET pin returns to VIH, the system can read data tRH.  
6.1.8 Output Disable Mode  
When the #OE input is at VIH, output from the device is disabled. The output pins are set in the high  
impedance state.  
6.1.9 Autoselect Mode  
The AUTOSELECT mode offers manufacturer and device identification, as well as sector protection  
verification, through identifier codes output on DQ0-DQ7. This mode is primarily intended for  
programming equipment to automatically match a device to be programmed with its corresponding  
programming algorithm. However, the AUTOSELECT codes can also be accessed in-system through  
the command register.  
When using programming equipment, the AUTOSELECT mode requires VID (8.5V to 12.5V) on  
address pins A9. Address pins A6, A1, and A0 must be as shown in table. In addition, when verifying  
sector protection, the sector address must appear on the appropriate highest order address bits.  
When all necessary bits have been set as required, the programming equipment may then read the  
corresponding identifier code on DQ0-DQ7.  
6.1.10 Sector/Sector Block Protection and Unprotection  
The hardware sector protection feature disables both program and erasure operations in any sectors.  
The hardware sector Unprotection feature re-enables both program and erasure operations in  
previously protected sectors. Sector Protection/Unprotection can be implemented through two  
methods.  
The primary method requires VID on the #RESET pin, and can be implemented either in-system or through  
programming equipment. This method uses standard microprocessor bus cycle timing.  
The alternate method intended only for programming equipment requires VID on address pin A9 and #OE. It  
is possible to determine whether a sector is protected or unprotected. See the Application Note for detail  
information.  
Publication Release Date: December 27, 2005  
- 9 -  
Revision A4  
 

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