Datasheet > W144

W144

更新时间： 2024-01-21 00:21:42

品牌	Logo	应用领域
SPECTRALINEAR		/
页数	文件大小	规格书
13页	201K
描述
440BX AGPset Spread Spectrum Frequency Synthesizer

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技术参数
数据手册

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W144 技术参数

是否Rohs认证：	符合	生命周期：	Active
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8541.40.20.00	风险等级：	5.77
其他特性：	HIGH RELIABILITY	颜色：	YELLOW
配置：	SINGLE	最大正向电流：	0.03 A
透镜类型：	DIFFUSED	标称发光强度：	3.0 mcd
安装特点：	RADIAL MOUNT	功能数量：	1
端子数量：	2	最高工作温度：	85 °C
最低工作温度：	-40 °C	光电设备类型：	SINGLE COLOR LED
总高度：	7 mm	包装方法：	BULK
峰值波长：	590 nm	形状：	RECTANGULAR
尺寸：	3.9 mm	表面贴装：	NO
端子节距：	2.54 mm	视角：	110 deg
Base Number Matches：	1

W144 数据手册

W144

Table 4. Byte Writing Sequence (continued)

Byte

Sequence

Byte Name

Data Byte 0

Bit Sequence

Byte Description

Refer to Table 5

The data bits in Data Bytes 0–7 set internal W144 registers that control

device operation. The data bits are only accepted when the Address Byte

bit sequence is 11010010, as noted above. For description of bit control

functions, refer to Table 5, Data Byte Serial Configuration Map.

Data Byte 1

Data Byte 2

Data Byte 3

Data Byte 4

Data Byte 5

Data Byte 6

Data Byte 7

Writing Data Bytes

Table 6 details additional frequency selections that are

available through the serial data interface.

Each bit in Data Bytes 0–7 controls a particular device function

except for the “reserved” bits, which must be written as a logic

0. Bits are written MSB (most significant bit) first, which is bit 7.

Table 5 gives the bit formats for registers located in Data Bytes

0–7.

Table 7 details the select functions for Byte 0, bits 1 and 0.

Table 5. Data Bytes 0-7 Serial Configuration Map

Affected Pin

Bit Control

Bit(s)

Pin No.

Pin Name

Control Function

Default

Data Byte 0

–

(Reserved)

SEL_2

–

See Table 6

SEL_1

SEL_0

Hardware/Software Frequency Select

SEL_3

Hardware

Software

See Table 6

1–0

Bit 1Bit 0Function (See Table 7 for function details)

00Normal Operation

01(Reserved)

10Spread Spectrum On

11All Outputs Three-stated

Data Byte 1

–

(Reserved)

–

(Reserved)

–

(Reserved)

–

(Reserved)

–

SDRAM_F

–

Clock Output Disable

(Reserved)

Low

–

Active

–

CPU1

CPU_F

Clock Output Disable

Low

Active

Rev 1.0,November 21, 2006

Page 6 of 13

1...3 4 567 8 9...13

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