Datasheet > VSC9142UK

VSC9142UK

更新时间： 2024-01-15 01:48:00

品牌	Logo	应用领域
VITESSE		/
页数	文件大小	规格书
42页	441K
描述
Clock Recovery Circuit, 1-Func, PBGA320, TBGA-320

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技术参数
数据手册

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VSC9142UK 技术参数

生命周期：	Transferred	零件包装代码：	BGA
包装说明：	LBGA,	针数：	320
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.82	JESD-30 代码：	S-PBGA-B320
长度：	25 mm	功能数量：	1
端子数量：	320	最高工作温度：	90 °C
最低工作温度：	-24 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	LBGA	封装形状：	SQUARE
封装形式：	GRID ARRAY, LOW PROFILE	认证状态：	Not Qualified
座面最大高度：	1.55 mm	标称供电电压：	1.8 V
表面贴装：	YES	电信集成电路类型：	ATM/SONET/SDH CLOCK RECOVERY CIRCUIT
温度等级：	OTHER	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
宽度：	25 mm	Base Number Matches：	1

VSC9142UK 数据手册

VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Datasheet

STS-48c Packet/ATM Over SONET/SDH Device

With Integrated Mux/Demux and Clock and Data Recovery

VSC9142

Integrated PHY Block Diagram

32:1

Parallel-to-Serial

1:32

Serial-to-Parallel

RLINSER+/-

TLOUTSER+/-

TLCLKSER+/-

to Tx Core Logic

to Rx Core Logic

78 MHz

2.5 GHz

78 MHz

CRULOCKDET

CRUREFCLK+/-

Timing Generator

PFD

Timing Generator

2.5 GHz

CRUFILTER+

CRUFILTER-

VCO

CMUFILTER+

CMUFILTER-

CMUREFSEL

CMULOCKDET

PFD

LOOPTIMING

Recovered Clock

From Rx CRU

CMUREFCLK+/-

78 MHz

155 MHz

311 MHz

622 MHz

78 MHz

155 MHz

311 MHz

622 MHz

Functional Overview

The VSC9142 is a dual mode SONET/SDH to Packet/ATM framing device that integrates the physical

layer components of 2.5 Gbps clock and data recovery and serialization/deserialization into a single device. In

the Packet over SONET (POS) mode, this device can be used in equipment interconnecting IP/PPP/HDLC data

over public or private SONET/SDH networks. Similarly, in the ATM over SONET (ATM) mode, this device

can be used in equipment interconnecting ATM switches. In addition, the VSC9142 can be used in various

applications involving LAPS (X.85/Y.1321) and Ethernet over SONET/SDH protocols.

Features of the VSC9142 include: Full insertion/extraction of the transport overhead, bit error rate and

extensive SONET/packet/cell performance monitoring, packet/cell filtering and discarding functionalities,

transmit and receive, JTAG TAP controller, and an 8-bit CPU interface with 8 general purpose I/O ports.

The high-speed component provides data and clock in the transmit direction, and selectable reference clock

frequencies and sources for both the transmit and receive directions. The VSC9142 can facilitate both internal

and external looptiming applications and also provides a 4-bit LVDS interface in both transmit and receive

direction for use in STS-192 applications. When using the 4-bit interface, the serializing/deserializing blocks of

the VSC9142 can be shut down for power savings.

This highly integrated device provides a complete low-power physical layer solution on a single chip for

Packet/ATM over SONET/SDH at the STS-48 rate.

Page 2

VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

G52319-0, Rev. 3.1

6/12/00

123 4 5 6 7...42

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