Datasheet > VSC9142UK

VSC9142UK

更新时间： 2024-02-17 08:09:08

品牌	Logo	应用领域
VITESSE		/
页数	文件大小	规格书
42页	441K
描述
Clock Recovery Circuit, 1-Func, PBGA320, TBGA-320

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技术参数
数据手册

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VSC9142UK 技术参数

生命周期：	Transferred	零件包装代码：	BGA
包装说明：	LBGA,	针数：	320
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.82	JESD-30 代码：	S-PBGA-B320
长度：	25 mm	功能数量：	1
端子数量：	320	最高工作温度：	90 °C
最低工作温度：	-24 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	LBGA	封装形状：	SQUARE
封装形式：	GRID ARRAY, LOW PROFILE	认证状态：	Not Qualified
座面最大高度：	1.55 mm	标称供电电压：	1.8 V
表面贴装：	YES	电信集成电路类型：	ATM/SONET/SDH CLOCK RECOVERY CIRCUIT
温度等级：	OTHER	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
宽度：	25 mm	Base Number Matches：	1

VSC9142UK 数据手册

VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Datasheet

STS-48c Packet/ATM Over SONET/SDH Device

With Integrated Mux/Demux and Clock and Data Recovery

VSC9142

• The 48 byte information field is scrambled with a self-synchronizing descrambler polynomial 1 + x .

Scrambling can be enabled/disabled.

• The HEC generator performs a CRC-8 calculation over the first four header octets using the generating

polynomial 1 + x + x + x . The coset polynomial 1 + x + x +x can be added to the result. The HEC

is optionally inserted into the fifth octet of the header of cells read from the Tx FIFO.

• The Tx FIFO can accomodate storage of eight ATM cells.

Transmit Packet Processor (TPP)

• The inserted HDLC Flag Sequence byte and the minimum number of Flag Sequence bytes separating

HDLC frames are programmable.

• The insertion of the Address and Control fields can be controlled by the HDLC Address-and-Control-

Field-Compression mechanism.

• The Address Field inserted after the beginning Flag Sequence is programmable.

• The Control Field inserted after the the Address Field is programmable.

• The Frame Check Sequence (FCS) can be generated using either a 16-bit, CRC-CCITT generating poly-

nomial 1 + x + x + x , or a 32-bit CRC-32 generating polynomial 1 + x + x + x + x + x + x + x

+ x + x + x + x + x + x + x .

• Octet Stuffing, or “escaping”, can be applied after the FCS generation and partial scrambling, if enabled.

The Control Escape byte and the Octet Stuffing Masking byte are programmable. The Asyc-Control-

Character-Map (ACCM) can accommodate a maximum of 5 byte values. Each value can be individually

enabled/disabled.

• The transmitted data is scrambled with a self-synchronizing scrambler (SSS) polynomial 1 + x . Full

and/or partial scrambling can be independently enabled/disabled.

• The PPP Protocol Field can be generated internally or extracted from the transmit FIFO. The size and

value of the inserted Protocol Field are programmable when generated internally.

• The Tx FIFO is programmable in the range from 1 to 4095 words or 16380 bytes of data storage. All

valid packet bytes stored in the Tx FIFO are read out and mapped into the PPP Protocol/Information

Fields of generated PPP/HDLC frames.

• Two Tx PIF packet transfer modes are supported: packet transfer mode and word transfer mode.

• The TXF_ERR signal is provided to force insertion of errors into the FCS, or to force abort the transmit-

ted HDLC frame.

• It is possible to force XOR'ing of the transmitted Address, Control or Protocol Fields with a programma-

ble mask value via the CPU interface for diagnostic purposes.

• The following statistics are provided in the performance monitoring 32-bit counters:

• Bytes read from Tx FIFO

• Transmitted good HDLC frames (non-aborted, non-FCS errored)

G52319-0, Rev. 3.1

VITESSE SEMICONDUCTOR CORPORATION

Page 7

6/12/00

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

1...4 5 678 9 10...42

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