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VSC9182-UG PDF预览

VSC9182-UG

更新时间: 2024-09-18 21:03:19
品牌 Logo 应用领域
美高森美 - MICROSEMI 电信电信集成电路
页数 文件大小 规格书
40页 990K
描述
Digital Time Switch, PBGA480, TBGA-480

VSC9182-UG 技术参数

生命周期:Contact Manufacturer包装说明:BGA,
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.73JESD-30 代码:S-PBGA-B480
长度:37.5 mm功能数量:1
端子数量:480封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装形状:SQUARE
封装形式:GRID ARRAY认证状态:Not Qualified
座面最大高度:1.925 mm标称供电电压:3.3 V
表面贴装:YES电信集成电路类型:DIGITAL TIME SWITCH
端子形式:BALL端子节距:1.27 mm
端子位置:BOTTOM宽度:37.5 mm
Base Number Matches:1

VSC9182-UG 数据手册

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VSC9182  
Data Sheet  
64x64 STS-12/STM-4 TSI Switch Fabric  
FEATURES  
• 64x64 STS-12/STM-4 TSI Switch with Non-  
• AIS and Unequipped Signal Insertion, LOS Detec-  
tion, Input Parity Checking and Output Parity Inser-  
tion; Scrambling and Descrambling  
blocking 768x768 STS-1 Switch Matrix  
• Supports Both Multicast and Broadcast  
• Hitless Reconfiguration of TSI Mapping  
• Single +3.3V Power Supply  
• Serial LVDS 622Mb/s High-Speed Interface  
with PECL/CML Compatibility and Retiming  
• Compliant with Relevant SONET/SDH Require-  
ments as Stated in ANSI T1.105, Bellcore GR-253-  
CORE and ITU-T G.707  
• 50MHz 11-Bit Microprocessor Interface  
• IEEE P1149.1 Test Access Port  
• Compatible with VSC918x Pointer Processors  
• Thermally-Enhanced 37.5mm 480 BGA Package  
• Integrated Clock Synthesis with a Choice of  
Two Reference Frequencies  
GENERAL DESCRIPTION  
The VSC9182 is a 64x64 STS-12/STM-4 Time Slot Interchange Switch IC for Cross Connection and Ring Protection  
Switching of STS(n) tributaries. All STS-12/STM-4 inputs and outputs are differential serial signals running at  
622.08Mb/s for efficiency in switch card and system backplane design. Using the STS-192/STM-64 Pointer  
Processor and Frame Aligner IC (VSC9186) and four VSC9182 devices in parallel, a 16x16 STS-192/STM-64 switch  
can be constructed.  
BLOCK DIAGRAM  
indexer  
SYNCP/N  
FOSYNCP/N  
input  
backplane  
interfaces  
(64)  
output  
backplane  
interfaces  
(64)  
Interconnection  
Matrix  
and Storage  
Data  
Data  
RXD[63..0]+/-  
TXD[63..0]+/-  
Clock  
Clock  
Synthesis  
PLL  
Test  
Interface  
Control  
Control  
CPU  
Interface  
SYSCLKP/N  
G52289, Rev 4.3  
12/3/02  
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012  
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com  
Internet: www.vitesse.com  
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