Datasheet > VSC9142UK

VSC9142UK

更新时间： 2024-02-07 15:52:43

品牌	Logo	应用领域
VITESSE		/
页数	文件大小	规格书
42页	441K
描述
Clock Recovery Circuit, 1-Func, PBGA320, TBGA-320

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技术参数
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VSC9142UK 技术参数

生命周期：	Transferred	零件包装代码：	BGA
包装说明：	LBGA,	针数：	320
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.82	JESD-30 代码：	S-PBGA-B320
长度：	25 mm	功能数量：	1
端子数量：	320	最高工作温度：	90 °C
最低工作温度：	-24 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	LBGA	封装形状：	SQUARE
封装形式：	GRID ARRAY, LOW PROFILE	认证状态：	Not Qualified
座面最大高度：	1.55 mm	标称供电电压：	1.8 V
表面贴装：	YES	电信集成电路类型：	ATM/SONET/SDH CLOCK RECOVERY CIRCUIT
温度等级：	OTHER	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
宽度：	25 mm	Base Number Matches：	1

VSC9142UK 数据手册

VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Datasheet

STS-48c Packet/ATM Over SONET/SDH Device

With Integrated Mux/Demux and Clock and Data Recovery

VSC9142

• The byte value used to identify the HDLC Flag Sequence is programmable.

• The detection and discarding of invalid frames are programmable.

• The expected Control Escape byte value and the Octet Destuffing Masking byte are programmable.

• The expected Address and Control Field values are programmable.

• The Protocol Field declaration and processing is programmable.

• The Abort Sequence is detected in the incoming HDLC frames.

• The received Frame Check Sequence (FCS) field is verified. The FCS checksum is calculated using either

a 16-bit, CRC-CCITT generating polynomial 1 + x + x + x , or a 32-bit, CRC-32 generating polyno-

mial 1 + x + x + x + x + x + x + x + x + x + x + x + x + x + x .

• The received data is descrambled with the self synchronizing scrambler (SSS) polynomial 1 + x . Full

and/or partial descrambling can be independently enabled/disabled.

• Long and short packet checking are provided and are programmable.

• Self Describing Padding is supported and programmable.

• The storage of the PPP Protocol Field in the Rx FIFO may be enabled/disabled.

• The size of the Rx FIFO size is 4095 words, which may accommodate storage for a total of 16380 PPP

Protocol/Information Field bytes.

• The definition of received “errored” HDLC frames is programmable. For these errored HDLC frames two

different procedures can be applied.

• A filtering function is provided to perform packet discartion and error marking based on a set of program-

mable labels. There are four programmable label matching triggers, and one compliment word matching

trigger that functions the packet discard and TERR marking.

• The following statistics are provided in the performance monitoring 32-bit counters:

• Received Aborted HDLC frames

• Received FCS errored HDLC frames

• Received Empty HDLC frames

• Received HDLC frames where Address-and-Control-Field-Compression was found

• Received Long packets

• Received Short packets

• Received Invalid Frames

• Received bytes pre-octet destuffing

• Received bytes post-octet destuffing

• Received number of frames excluding Invalid Frames

• Packets discarded by label filtering

• Packets error-marked by label filtering

• Packets stored in the Rx FIFO

G52319-0, Rev. 3.1

VITESSE SEMICONDUCTOR CORPORATION

Page 5

6/12/00

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

1 2 3 456 7 8...42

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