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VSC8244HG PDF预览

VSC8244HG

更新时间: 2024-02-10 08:45:35
品牌 Logo 应用领域
美国微芯 - MICROCHIP 以太网:16GBASE-T电信电信集成电路
页数 文件大小 规格书
121页 907K
描述
Ethernet Transceiver

VSC8244HG 技术参数

生命周期:Obsolete包装说明:HBGA, BGA260,18X18,40
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.67数据速率:1000000 Mbps
JESD-30 代码:S-PBGA-B260长度:19 mm
功能数量:4端子数量:260
收发器数量:4最高工作温度:100 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:HBGA封装等效代码:BGA260,18X18,40
封装形状:SQUARE封装形式:GRID ARRAY, HEAT SINK/SLUG
电源:1.2,3.3 V认证状态:Not Qualified
座面最大高度:2 mm子类别:Network Interfaces
标称供电电压:1.2 V表面贴装:YES
技术:CMOS电信集成电路类型:ETHERNET TRANSCEIVER
温度等级:OTHER端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
宽度:19 mmBase Number Matches:1

VSC8244HG 数据手册

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VSC8244  
Data Sheet  
12 Twisted Pair Interface..................................................................................................................................... 33  
12.1 Twisted Pair Autonegotiation (IEEE802.3 Clause 28) ...............................................................................................33  
12.2 Twisted Pair Auto MDI/MDI-X Function .....................................................................................................................34  
12.3 Auto MDI/MDI-X in Forced 10/100 Link Speeds .......................................................................................................34  
12.4 Twisted Pair Link Speed Downshift ..........................................................................................................................34  
13 Transformerless Ethernet Operation for PICMG 2.16 and 3.0 IP-based Backplanes............................... 35  
14 Serial Management Interface (SMI)............................................................................................................... 35  
14.1 SMI Interrupt .............................................................................................................................................................36  
15 Parallel LED Interface..................................................................................................................................... 38  
16 Serial LED Output........................................................................................................................................... 41  
17 Test Mode Interface (JTAG) ........................................................................................................................... 42  
17.1 Supported Instructions and Instruction Codes ..........................................................................................................43  
17.2 Boundary-Scan Register Cell Order .........................................................................................................................44  
18 VeriPHY Cable Diagnostics ........................................................................................................................... 45  
18.1 Coupling Between Cable Pairs .................................................................................................................................45  
18.2 Cable Pair Termination ..............................................................................................................................................45  
18.3 Cable Length ............................................................................................................................................................45  
18.4 Using VeriPHY in normal operating mode ................................................................................................................45  
19 ActiPHY Power Management......................................................................................................................... 46  
19.1 Operation in ActiPHY Mode ......................................................................................................................................46  
19.2 Low power state ........................................................................................................................................................47  
19.3 LP Wake up state ......................................................................................................................................................47  
19.4 Normal operating state .............................................................................................................................................47  
20 Ethernet In-line Powered Device Support.................................................................................................... 48  
20.1 Cisco In-Line Powered Device Detection ..................................................................................................................48  
20.2 In-Line Power Ethernet Switch Diagram ...................................................................................................................48  
20.3 In-Line Powered Device Detection (Cisco Method) ..................................................................................................49  
20.4 IEEE 802.3af (DTE Power via MDI) ..........................................................................................................................49  
21 Advanced Test Modes.................................................................................................................................... 49  
21.1 Ethernet Packet Generator (EPG) ............................................................................................................................49  
21.2 CRC Counter ............................................................................................................................................................49  
21.3 Far-end Loopback .....................................................................................................................................................50  
21.4 Near-end Loopback ..................................................................................................................................................50  
21.5 Connector Loopback .................................................................................................................................................51  
22 Initialization & Configuration......................................................................................................................... 52  
22.1 Resets .......................................................................................................................................................................52  
22.2 Power-Up Sequence .................................................................................................................................................52  
22.3 CMODE Pin Configuration ........................................................................................................................................52  
22.4 EEPROM Interface ...................................................................................................................................................55  
5 of 7  
VMDS-10108 Revision 4.1  
7
June 2006  

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