DATA SHEET
MOS INTEGRATED CIRCUIT
µPD703014A, 703014AY, 703014B, 703014BY, 703015A,
703015AY, 703015B, 703015BY, 703017A, 703017AY
V850/SA1TM
32-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
The µPD703014A, 703014AY, 703014B, 703014BY, 703015A, 703015AY, 703015B, 703015BY, 703017A, and
703017AY (V850/SA1) are 32-bit single-chip V850 FamilyTM microcontrollers that include the peripheral functions
such as ROM/RAM, timer/counters, serial interfaces, an A/D converter, and a DMA controller.
In addition to its high real-time responsiveness and one-clock-pitch execution of instructions, the V850/SA1
includes a hardware multiplier for multiplication instructions, saturation instructions, and bit manipulation instructions,
all of which are instructions suited to digital servo control applications. As a real-time control system, this device
provides a high-level cost performance ideal for applications ranging from low-power camcorders and other AV
equipment to portable telephone equipment such as cellular phones and personal handyphone systems (PHS).
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
V850/SA1 User’s Manual Hardware:
U12768E
V850 Family User’s Manual Architecture: U10243E
FEATURES
{ Number of instructions: 74
{ Memory space:
{ Minimum instruction execution time:
58.8 ns (@ 17 MHz operation with main clock (fXX))
50 ns (@ 20 MHz operation with main clock (fXX))
30.5 µs (@ 32.768 kHz operation with subclock (fXT))
{ General-purpose registers: 32 bits × 32 registers
{ Instruction set:
16 MB linear address space
Memory block allocation function: 2 MB per block
{ External bus interface: 16-bit data bus
Address bus: Separate output enabled
{ Interrupts and exception
External: 8, internal: 23, exception: 1
{ I/O lines Total: 85
Signed multiplication, saturation operations, 32-bit
shift instructions, bit manipulation instructions,
load/store instructions
{ Timer/counters
16-bit timer: 2 channels
{ Internal memory
8-bit timer:
4 channels
• Mask ROM:
{ Watch timer: 1 channel
64 KB
{ Watchdog timer: 1 channel
{ Serial interface (SIO)
(µPD703014A, 703014AY, 703014B, 703014BY)
128 KB
Asynchronous serial interface (UART)
Clocked serial interface (CSI)
I2C bus interface
(µPD703015A, 703015AY, 703015B, 703015BY)
256 KB (µPD703017A, 703017AY)
• RAM:
(µPD703014AY, 703014BY, 703015AY,
703015BY, 703017AY)
4 KB
(µPD703014A, 703014AY, 703014B, 703014BY,
703015A, 703015AY, 703015B, 703015BY)
8 KB (µPD703017A, 703017AY)
{ A/D converter: 12 channels
{ DMA controller: 3 channels
{ RTP: 8 bits × 1 channel or 4 bits × 2 channels
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. U14526EJ3V0DS00 (3rd edition)
The mark shows major revised points.
Date Published June 2001 N CP(K)
Printed in Japan
©
2000