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UPD703017AYS1-XXX-YJC

更新时间： 2024-11-08 08:51:39
品牌 Logo 应用领域
日电电子 - NEC 微控制器
页数 文件大小 规格书
48页 305K
描述
Microcontroller, 32-Bit, MROM, 20MHz, MOS, PBGA121, 12 X 12 MM, PLASTIC, FBGA-121

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UPD703017AYS1-XXX-YJC 数据手册

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DATA SHEET  
MOS INTEGRATED CIRCUIT  
µ
PD703014A, 703014AY, 703015A,  
703015AY, 703017A, 703017AY  
V850/SA1TM  
32-/16-BIT SINGLE-CHIP MICROCONTROLLER  
DESCRIPTION  
The µPD703014A, 703014AY, 703015A, 703015AY, 703017A, and 703017AY (V850/SA1) are 32-/16-bit single-  
chip microcontrollers that include the CPU core of the V850 FamilyTM, and peripheral functions such as ROM/RAM,  
timer/counters, serial interfaces, an A/D converter, a timer, and a DMA controller.  
In addition to its high real-time responsiveness and one-clock-pitch execution of instructions, the V850/SA1  
includes a hardware multiplier for multiplication instructions, saturation instructions, and bit manipulation instructions,  
all of which are instructions suited to digital servo control applications. As a real-time control system, this device  
provides a high-level cost performance ideal for applications ranging from low-power camcorders and other AV  
equipment to portable telephone equipment such as cellular phones and personal handyphone systems (PHS).  
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before  
designing.  
V850/SA1 User’s Manual Hardware:  
U12768E  
V850 Family User’s Manual Architecture: U10243E  
FEATURES  
{ Number of instructions: 74  
{ Interrupts and exception  
{ Minimum instruction execution time:  
External: 8, internal: 23, exception: 1  
{ I/O lines Total: 85  
59 ns (@ 17 MHz operation with main system clock (fXX))  
50 ns (@ 20 MHz operation with main system clock (fXX))  
{ Timer/counters  
30.5 µs (@ 32.768 kHz operation with subsystem clock (fXT))  
16-bit timer: 2 channels  
{ General-purpose registers: 32 bits × 32 registers  
{ Instruction set:  
8-bit timer:  
4 channels  
{ Watch timer: 1 channel  
Signed multiplication, saturation operations, 32-bit  
shift instructions, bit manipulation instructions,  
load/store instructions  
{ Watchdog timer: 1 channel  
{ Serial interface (SIO)  
Asynchronous serial interface (UART)  
{ Memory space:  
Clocked serial interface (CSI)  
I2C bus interface  
16 MB linear address space  
Memory block allocation function: 2 MB per block  
{ External bus interface: 16-bit data bus  
Address bus: Separate output enabled  
{ Internal memory  
(µPD703014AY, 703015AY, 703017AY)  
{ A/D converter: 12 channels  
{ DMA controller: 3 channels  
{ RTP: 8 bits × 1 channel or 4 bits × 2 channels  
{ Power-saving functions: HALT/IDLE/STOP modes  
{ Packages: 100-pin plastic LQFP (14 × 14)  
121-pin plastic FBGA (12 × 12)  
Mask ROM: 64 KB (µPD703014A, 703014AY)  
128 KB (µPD703015A, 703015AY)  
256 KB (µPD703017A, 703017AY)  
RAM: 4 KB  
(µPD703014A, 703014AY, 703015A, 703015AY)  
8 KB (µPD703017A, 703017AY)  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all devices/types available in every country. Please check with local NEC representative for  
availability and additional information.  
Document No. U14526EJ1V0DS00 (1st edition)  
Date Published February 2000 N CP(K)  
Printed in Japan  
©
2000  
1234567...48

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