5秒后页面跳转
UPD485505 PDF预览

UPD485505

更新时间: 2024-10-13 22:52:35
品牌 Logo 应用领域
日电电子 - NEC /
页数 文件大小 规格书
20页 174K
描述
LINE BUFFER 5K-WORD BY 8-BIT

UPD485505 数据手册

 浏览型号UPD485505的Datasheet PDF文件第2页浏览型号UPD485505的Datasheet PDF文件第3页浏览型号UPD485505的Datasheet PDF文件第4页浏览型号UPD485505的Datasheet PDF文件第5页浏览型号UPD485505的Datasheet PDF文件第6页浏览型号UPD485505的Datasheet PDF文件第7页 
DATA SHEET  
MOS INTEGRATED CIRCUIT  
µPD485505  
LINE BUFFER  
5K-WORD BY 8-BIT  
Description  
The µPD485505 is a 5,048 words by 8 bits high speed FIFO (First In First Out) line buffer. Its CMOS static circuitry  
provides high speed access and low power consumption.  
The µPD485505 can be used for one line delay and time axis conversion in high speed facsimile machines and  
digital copiers.  
Moreover, the µPD485505 can execute read and write operations independently on an asynchronous basis. Thus  
the µPD485505 is suitable as a buffer for data transfer between units with different transfer rates and as a buffer for  
the synchronization of multiple input signals. There are three versions, E, K, P, and L. This data sheet can be applied  
to the version P and L. These versions operate with different specifications. Each version is identified with its lot  
number (refer to 7. Example of Stamping).  
Features  
5,048 words by 8 bits  
Asynchronous read/write operations available  
Variable length delay bits; 21 to 5,048 bits (Cycle time: 25 ns)  
15 to 5,048 bits (Cycle time: 35 ns)  
Power supply voltage VCC = 5.0 V ± 0.5 V  
Suitable for sampling one line of A3 size paper (16 dots/mm)  
All input/output TTL compatible  
3-state output  
Full static operation; data hold time = infinity  
Ordering Information  
Part Number  
µPD485505G-25  
µPD485505G-35  
R/W Cycle Time  
Package  
25 ns  
35 ns  
24-pin plastic SOP  
(11.43 mm (450))  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all devices/types available in every country. Please check with local NEC representative for availability  
and additional information.  
Document No. M10059EJ7V0DSJ1 (7th edition)  
Date Published December 2000 N CP(K)  
Printed in Japan  
The mark shows major revised points.  
1994,1996  
©

与UPD485505相关器件

型号 品牌 获取价格 描述 数据表
UPD485505G-25 NEC

获取价格

LINE BUFFER 5K-WORD BY 8-BIT
UPD485505G-25-A NEC

获取价格

FIFO, 5KX8, 18ns, Synchronous, CMOS, PDSO24, 0.450 INCH, PLASTIC, SOP-24
UPD485505G-25-E2 NEC

获取价格

5KX8 OTHER FIFO, 18ns, PDSO24, 11.43 MM, PLASTIC, SOP-24
UPD485505G-25-E2-A NEC

获取价格

FIFO, 5KX8, 18ns, Synchronous, CMOS, PDSO24, 11.43 MM, PLASTIC, SOP-24
UPD485505G-27 ETC

获取价格

Field/Frame/Line Memory
UPD485505G-35 NEC

获取价格

LINE BUFFER 5K-WORD BY 8-BIT
UPD485505G-35-A NEC

获取价格

暂无描述
UPD485505GU-25 ETC

获取价格

Field/Frame/Line Memory
UPD485505GU-35 ETC

获取价格

Field/Frame/Line Memory
UPD485505V-25 ETC

获取价格

Field/Frame/Line Memory