Datasheet > UPD485506

UPD485506

更新时间： 2024-10-13 22:52:35

品牌	Logo	应用领域
日电电子 - NEC		/
页数	文件大小	规格书
24页	232K
描述
LINE BUFFER 5K-WORD BY 16-BIT/10K-WORD BY 8-BIT

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中文翻译

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数据手册

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UPD485506 数据手册

DATA SHEET

MOS INTEGRATED CIRCUIT

µPD485506

LINE BUFFER

5K-WORD BY 16-BIT/10K-WORD BY 8-BIT

Description

The µPD485506 is a high speed FIFO (First In First Out) line buffer. Word organization can be changed either

5,048 words by 16 bits or 10,096 words by 8 bits. Its CMOS static circuitry provides high speed access and low power

consumption.

The µPD485506 can be used for one line delay and time axis conversion in high speed facsimile machines and

digital copiers.

Moreover, the µPD485506 can execute read and write operations independently on an asynchronous basis. Thus

the µPD485506 is suitable as a buffer for data transfer between units with different transfer rates and as a buffer for

the synchronization of multiple input signals.

There are four versions, E, K, P, X and L. This data sheet can be applied to the version X and L. These versions

operate with different specifications. Each version is identified with its lot number (refer to 7. Example of Stamping).

Features

•

5,048 words by 16 bits (Word mode) /10,096 words by 8 bits (Byte mode)

Asynchronous read/write operations available

Variable length delay bits; 21 to 5,048 bits or 10,096 bits (Cycle time: 25 ns)

15 to 5,048 bits or 10,096 bits (Cycle time: 35 ns)

Power supply voltage V^CC= 5.0 V ±0.5 V

•

Suitable for sampling two lines of A3 size paper (16 dots/mm)

All input/output TTL compatible

3-state output

Full static operation; data hold time = infinity

Ordering Information

Part Number

R/W Cycle Time

25 ns

Package

µPD485506G5-25-7JF

µPD485506G5-35-7JF

44-pin plastic TSOP (II) (10.16 mm (400))

35 ns

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for availability

and additional information.

Document No. M10060EJ7V0DSJ1 (7th edition)

Date Published December 2000 N CP(K)

Printed in Japan

The mark shows major revised points.

1994

12 3 4 5 6 7...24

中文翻译

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与UPD485506相关器件

型号	品牌	获取价格	描述	数据表
UPD485506G5-25	ETC	获取价格	Field/Frame/Line Memory
UPD485506G5-25-7JF	NEC	获取价格	LINE BUFFER 5K-WORD BY 16-BIT/10K-WORD BY 8-BIT
UPD485506G5-25-7JF-A	RENESAS	获取价格	5KX16 OTHER FIFO, 18ns, PDSO44, 0.400 INCH, PLASTIC, TSOP2-44
UPD485506G5-27	ETC	获取价格	Field/Frame/Line Memory
UPD485506G5-35	ETC	获取价格	Field/Frame/Line Memory
UPD485506G5-35-7JF	NEC	获取价格	LINE BUFFER 5K-WORD BY 16-BIT/10K-WORD BY 8-BIT
UPD485506G5-35-7JF-A	NEC	获取价格	FIFO, 5KX16, 25ns, Synchronous, CMOS, PDSO44, 10.16 MM, LEAD FREE, PLASTIC, TSOP2-44
UPD48576118F1-E24-DW1-A	RENESAS	获取价格	576M-BIT Low Latency DRAM Separate I/O
UPD48576209F1	RENESAS	获取价格	576M-BIT Low Latency DRAM
UPD48576209F1-E24-DW1-A	RENESAS	获取价格	576M-BIT Low Latency DRAM

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