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UPD44645082F5-E50-FQ1-A PDF预览

UPD44645082F5-E50-FQ1-A

更新时间: 2024-10-30 20:08:23
品牌 Logo 应用领域
日电电子 - NEC 时钟静态存储器内存集成电路
页数 文件大小 规格书
40页 370K
描述
QDR SRAM, 8MX8, 0.45ns, CMOS, PBGA165, 15 X 17 MM, LEAD FREE, PLASTIC, BGA-165

UPD44645082F5-E50-FQ1-A 技术参数

是否Rohs认证: 符合生命周期:Transferred
包装说明:15 X 17 MM, LEAD FREE, PLASTIC, BGA-165Reach Compliance Code:compliant
风险等级:5.79最长访问时间:0.45 ns
JESD-30 代码:R-PBGA-B165JESD-609代码:e1
长度:17 mm内存密度:67108864 bit
内存集成电路类型:QDR SRAM内存宽度:8
功能数量:1端子数量:165
字数:8388608 words字数代码:8000000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:8MX8
封装主体材料:PLASTIC/EPOXY封装代码:LBGA
封装形状:RECTANGULAR封装形式:GRID ARRAY, LOW PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified座面最大高度:1.51 mm
最大供电电压 (Vsup):1.9 V最小供电电压 (Vsup):1.7 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:TIN SILVER COPPER端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:15 mm
Base Number Matches:1

UPD44645082F5-E50-FQ1-A 数据手册

 浏览型号UPD44645082F5-E50-FQ1-A的Datasheet PDF文件第2页浏览型号UPD44645082F5-E50-FQ1-A的Datasheet PDF文件第3页浏览型号UPD44645082F5-E50-FQ1-A的Datasheet PDF文件第4页浏览型号UPD44645082F5-E50-FQ1-A的Datasheet PDF文件第5页浏览型号UPD44645082F5-E50-FQ1-A的Datasheet PDF文件第6页浏览型号UPD44645082F5-E50-FQ1-A的Datasheet PDF文件第7页 
PRELIMINARY DATA SHEET  
MOS INTEGRATED CIRCUIT  
PD44645082, 44645092, 44645182, 44645362  
μ
72M-BIT QDRTM II SRAM  
2-WORD BURST OPERATION  
Description  
The μPD44645082 is a 8,388,608-word by 8-bit, the μPD44645092 is a 8,388,608-word by 9-bit, the μPD44645182 is a  
4,194,304-word by 18-bit and the μPD44645362 is a 2,097,152-word by 36-bit synchronous quad data rate static RAM  
fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.  
The μPD44645082, μPD44645092, μPD44645182 and μPD44645362 integrate unique synchronous peripheral  
circuitry and a burst counter. All input registers controlled by an input clock pair (K and K#) are latched on the positive  
edge of K and K#.  
These products are suitable for application which require synchronous operation, high speed, low voltage, high density  
and wide bit configuration.  
These products are packaged in 165-pin PLASTIC BGA.  
Features  
1.8 ± 0.1 V power supply  
165-pin PLASTIC BGA (15 x 17)  
HSTL interface  
PLL circuitry for wide output data valid window and future frequency scaling  
Separate independent read and write data ports with concurrent transactions  
100% bus utilization DDR READ and WRITE operation  
Two-tick burst for low DDR transaction size  
Two input clocks (K and K#) for precise DDR timing at clock rising edges only  
Two output clocks (C and C#) for precise flight time and clock skew matching-clock  
and data delivered together to receiving device  
Internally self-timed write control  
Clock-stop capability. Normal operation is restored in 1,024 cycles after clock is resumed.  
User programmable impedance output  
Fast clock cycle time : 4.0 ns (250 MHz), 5.0 ns (200 MHz)  
Simple control logic for easy depth expansion  
JTAG boundary scan  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all products and/or types are available in every country. Please check with an NEC Electronics  
sales representative for availability and additional information.  
Document No. M18231EJ2V0DS00 (2nd edition)  
Date Published February 2007 NS CP(N)  
Printed in Japan  
2006  
The mark <R> shows major revised points.  
The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field.  

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