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UPD44325094F5-E50-EQ2-A PDF预览

UPD44325094F5-E50-EQ2-A

更新时间： 2024-02-16 19:35:56
品牌 Logo 应用领域
日电电子 - NEC 存储内存集成电路静态存储器
页数 文件大小 规格书
36页 367K
描述
QDR SRAM, 4MX9, 0.45ns, CMOS, PBGA165, 13 X 15 MM, LEAD FREE, PLASTIC, BGA-165

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UPD44325094F5-E50-EQ2-A 技术参数

是否Rohs认证： 符合生命周期：Transferred
包装说明：13 X 15 MM, LEAD FREE, PLASTIC, BGA-165Reach Compliance Code：compliant
风险等级：5.77最长访问时间：0.45 ns
JESD-30 代码：R-PBGA-B165JESD-609代码：e1
长度：15 mm内存密度：37748736 bit
内存集成电路类型：QDR SRAM内存宽度：9
功能数量：1端子数量：165
字数：4194304 words字数代码：4000000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：4MX9
封装主体材料：PLASTIC/EPOXY封装代码：LBGA
封装形状：RECTANGULAR封装形式：GRID ARRAY, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
认证状态：Not Qualified座面最大高度：1.51 mm
最大供电电压 (Vsup)：1.9 V最小供电电压 (Vsup)：1.7 V
标称供电电压 (Vsup)：1.8 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：TIN SILVER COPPER端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：13 mm
Base Number Matches：1

UPD44325094F5-E50-EQ2-A 数据手册

 浏览型号UPD44325094F5-E50-EQ2-A的Datasheet PDF文件第4页浏览型号UPD44325094F5-E50-EQ2-A的Datasheet PDF文件第5页浏览型号UPD44325094F5-E50-EQ2-A的Datasheet PDF文件第6页浏览型号UPD44325094F5-E50-EQ2-A的Datasheet PDF文件第8页浏览型号UPD44325094F5-E50-EQ2-A的Datasheet PDF文件第9页浏览型号UPD44325094F5-E50-EQ2-A的Datasheet PDF文件第10页 
µPD44325084, 44325094, 44325184, 44325364  
Pin Identification  
Symbol  
Description  
A
Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the  
rising edge of K. All transactions operate on a burst of four words (two clock periods of bus activity). These  
inputs are ignored when device is deselected.  
D0 to Dxx  
Synchronous Data Inputs: Input data must meet setup and hold times around the rising edges of K and /K  
during WRITE operations. See Pin Configurations for ball site location of individual signals.  
x8 device uses D0 to D7.  
x9 device uses D0 to D8.  
x18 device uses D0 to D17.  
x36 device uses D0 to D35.  
Q0 to Qxx  
Synchronous Data Outputs: Output data is synchronized to the respective C and /C or to K and /K rising edges  
if C and /C are tied HIGH. This bus operates in response to /R commands. See Pin Configurations for ball site  
location of individual signals.  
x8 device uses Q0 to Q7.  
x9 device uses Q0 to Q8.  
x18 device uses Q0 to Q17.  
x36 device uses Q0 to Q35.  
/R  
Synchronous Read: When LOW this input causes the address inputs to be registered and a READ cycle to be  
initiated. This input must meet setup and hold times around the rising edge of K and is ignored on the  
subsequent rising edge of K.  
/W  
Synchronous Write: When LOW this input causes the address inputs to be registered and a WRITE cycle to be  
initiated. This input must meet setup and hold times around the rising edge of K and is ignored on the  
subsequent rising edge of K.  
/BWx  
/NWx  
Synchronous Byte Writes (Nibble Writes on x8): When LOW these inputs cause their respective byte or nibble  
to be registered and written during WRITE cycles. These signals must meet setup and hold times around the  
rising edges of K and /K for each of the two rising edges comprising the WRITE cycle. See Pin Configurations  
for signal to data relationships.  
K, /K  
C, /C  
Input Clock: This input clock pair registers address and control inputs on the rising edge of K, and registers data  
on the rising edge of K and the rising edge of /K. /K is ideally 180 degrees out of phase with K. All synchronous  
inputs must meet setup and hold times around the clock rising edges.  
Output Clock: This clock pair provides a user controlled means of tuning device output data. The rising edge of  
/C is used as the output timing reference for first and third output data. The rising edge of C is used as the  
output reference for second and fourth output data. Ideally, /C is 180 degrees out of phase with C. C and /C  
may be tied HIGH to force the use of K and /K as the output reference clocks instead of having to provide C and  
/C clocks. If tied HIGH, C and /C must remain HIGH and not be toggled during device operation.  
Synchronous Echo Clock Outputs. The rising edges of these outputs are tightly matched to the synchronous  
data outputs and can be used as a data valid indication. These signals run freely and do not stop when Q  
tristates.  
CQ, /CQ  
ZQ  
Output Impedance Matching Input: This input is used to tune the device outputs to the system data bus  
impedance. DQ and CQ output impedance are set to 0.2 x RQ, where RQ is a resistor from this bump to  
ground. This pin cannot be connected directly to GND or left unconnected.  
/DLL  
DLL Disable: When LOW, this input causes the DLL to be bypassed for stable low frequency operation.  
TMS  
TDI  
IEEE 1149.1 Test Inputs: 1.8V I/O levels. These balls may be left Not Connected if the JTAG function is not  
used in the circuit.  
TCK  
IEEE 1149.1 Clock Input: 1.8V I/O levels. This pin must be tied to VSS if the JTAG function is not used in the  
circuit.  
TDO  
VREF  
VDD  
IEEE 1149.1 Test Output: 1.8V I/O level.  
HSTL Input Reference Voltage: Nominally VDDQ/2. Provides a reference voltage for the input buffers.  
Power Supply: 1.8V nominal. See DC Characteristics and Operating Conditions for range.  
VDDQ  
Power Supply: Isolated Output Buffer Supply. Nominally 1.5V. 1.8V is also permissible. See DC Characteristics  
and Operating Conditions for range.  
VSS  
NC  
Power Supply: Ground  
No Connect: These signals are internally connected and appear in the JTAG scan chain as the logic level  
applied to the ball sites. These signals may be connected to ground to improve package heat dissipation.  
Preliminary Data Sheet M16784EJ1V0DS  
7
1...45678910...36

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