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UPD16732AXXX PDF预览

UPD16732AXXX

更新时间: 2024-11-06 19:57:11
品牌 Logo 应用领域
日电电子 - NEC 驱动接口集成电路
页数 文件大小 规格书
24页 173K
描述
Liquid Crystal Driver, 384-Segment, MOS, TCP-443

UPD16732AXXX 技术参数

是否Rohs认证: 不符合生命周期:Transferred
零件包装代码:DIE包装说明:DIE,
针数:443Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.41数据输入模式:PARALLEL
显示模式:DOT MATRIX接口集成电路类型:LIQUID CRYSTAL DISPLAY DRIVER
JESD-30 代码:R-XUUC-N443JESD-609代码:e0
复用显示功能:NO功能数量:1
区段数:384端子数量:443
最高工作温度:75 °C最低工作温度:-10 °C
封装主体材料:UNSPECIFIED封装代码:DIE
封装形状:RECTANGULAR封装形式:UNCASED CHIP
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
最大供电电压:3.6 V最小供电电压:2.3 V
标称供电电压:3 V电源电压1-最大:9 V
电源电压1-分钟:8 V电源电压1-Nom:8.5 V
表面贴装:YES技术:MOS
温度等级:COMMERCIAL EXTENDED端子面层:TIN LEAD
端子形式:NO LEAD端子位置:UPPER
处于峰值回流温度下的最长时间:NOT SPECIFIED最小 fmax:45 MHz
Base Number Matches:1

UPD16732AXXX 数据手册

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DATA SHEET  
MOS INTEGRATED CIRCUIT  
µ PD16732A, 16732B  
384-OUTPUT TFT-LCD SOURCE DRIVER  
(COMPATIBLE WITH 64-GRAY SCALES)  
The µ PD16732A, 16732B are a source driver for TFT-LCDs capable of dealing with displays with 64-gray scales.  
Data input is based on digital input configured as 6 bits by 6 dots (2 pixels), which can realize a full-color display of  
260,000 colors by output of 64 values γ -corrected by an internal D/A converter and 5-by-2 external power modules.  
Because the output dynamic range is as large as VSS2 + 0.1 V to VDD2 – 0.1 V, level inversion operation of the LCD’s  
common electrode is rendered unnecessary. Also, to be able to deal with dot-line inversion, n-line inversion and  
column line inversion when mounted on a single side, this source driver is equipped with a built-in 6-bit D/A converter  
circuit whose odd output pins and even output pins respectively output gray scale voltages of differing polarity.  
Assuring a maximum clock frequency of 65 MHz when driving at 3.0 V, 45 MHz when driving at 2.3 V, this driver is  
applicable to XGA-standard TFT-LCD panels and SXGA TFT-LCD panels by input display signal 2 systems (Clock  
divide).  
FEATURES  
CMOS level input (2.3 V to 3.6 V)  
384 Outputs  
Input of 6 bits (gradation data) by 6 dots  
Capable of outputting 64 values by means of 5-by-2 external power modules (10 units) and  
a D/A converter (R-DAC)  
Logic power supply voltage (VDD1) : 2.3 V to 3.6 V  
Driver power supply voltage (VDD2) : 8.5 ± 0.5 V  
High-speed data transfer: fMAX. = 65 MHz (internal data transfer speed when operating at VDD1 = 3.0 V)  
Output dynamic range VSS2 + 0.1 V to VDD2 – 0.1 V  
Apply for dot-line inversion, n-line inversion and column line inversion  
Output Voltage polarity inversion function (POL)  
Display data inversion function (POL2)  
Low power control function (LPC)  
ORDERING INFORMATION  
Part Number  
Package  
µ PD16732A,16732BN-×××  
TCP (TAB package)  
Remark The TCP’s external shape is customized. To order your TCP’s external shape, please contact a NEC  
salesperson.  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all devices/types available in every country. Please check with local NEC representative for  
availability and additional information.  
Document No. S13972EJ1V0DS00 (1st edition)  
Date Published March 1999 NS CP(K)  
Printed in Japan  
1999  

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