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UPD16738-XXX PDF预览

UPD16738-XXX

更新时间： 2024-11-06 14:45:23
品牌 Logo 应用领域
日电电子 - NEC 驱动接口集成电路
页数 文件大小 规格书
16页 147K
描述
Liquid Crystal Driver, 384-Segment, CMOS, DIE

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中文翻译

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UPD16738-XXX 技术参数

生命周期：Obsolete零件包装代码：DIE
包装说明：DIE,Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.84数据输入模式：PARALLEL
显示模式：DOT MATRIX接口集成电路类型：LIQUID CRYSTAL DISPLAY DRIVER
JESD-30 代码：R-XUUC-N复用显示功能：YES
功能数量：1区段数：384
最高工作温度：75 °C最低工作温度：-10 °C
封装主体材料：UNSPECIFIED封装代码：DIE
封装形状：RECTANGULAR封装形式：UNCASED CHIP
认证状态：Not Qualified最大供电电压：3.6 V
最小供电电压：2.7 V标称供电电压：3.3 V
电源电压1-最大：9 V电源电压1-分钟：7.5 V
电源电压1-Nom：8.5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL EXTENDED
端子形式：NO LEAD端子位置：UPPER
Base Number Matches：1

UPD16738-XXX 数据手册

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DATA SHEET  
MOS INTEGRATED CIRCUIT  
µPD16738  
384-OUTPUT TFT-LCD SOURCE DRIVER  
(COMPATIBLE WITH 64-GRAY SCALES )  
DESCRIPTION  
The µPD16738 is a source driver for TFT-LCDs capable of dealing with displays with 64-gray scales. Data input is based  
on digital input configured as 6 bits by 6 dots (2 pixels), which can realize a full-color display of 260,000 colors by output of 64  
values γ -corrected by an internal D/A converter and 5-by-2 external power modules. Because the output dynamic range is as  
large as VSS2+0.1 V to VDD2–0.1 V, level inversion operation of the LCD’s common electrode is rendered unnecessary. Also,  
to be able to deal with dot-line inversion, n-line inversion and column line inversion when mounted on a single side, this  
source driver is equipped with a built-in 6-bit D/A converter circuit whose odd output pins and even output pins respectively  
output gray scale voltages of differing polarity. Assuring a maximum clock frequency of 45 MHz when driving at 2.7 V, this  
driver is applicable to XGA-standard TFT-LCD panels.  
FEATURES  
• CMOS level input  
• 384 Outputs  
• Input of 6 bits (gradation data) by 6 dots  
• Capable of outputting 64 values by means of 5-by-2 external power modules (10 units) and  
a D/A converter  
+0.3  
–0.6  
+0.5  
• Logic power supply voltage (VDD1) : 3.3 V  
• Driver power supply voltage (VDD2) : 8.5 V  
V
V
–1.0  
• High-speed data transfer : fCLK = 45 MHz MAX. (internal data transfer speed when operating at VDD1 = 2.7 V)  
• Output dynamic range : VSS2 + 0.1 V to VDD2 – 0.1 V  
•
• Apply for dot-line inversion, n-line inversion and column line inversion  
• Output Voltage polarity inversion function (POL)  
• Display data inversion function (POL2)  
• Single bank arrangement is possible (Loaded with slim or bending TCP)  
ORDERING INFORMATION  
Part Number  
Package  
µPD16738N -×××  
TCP (TAB package)  
Remark The TCP’s external shape is customized. To order your TCP’s external shape, please contact a  
NEC salesperson.  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all devices/types available in every country. Please check with local NEC representative for  
availability and additional information.  
•
The mark shows major revised points.  
Document No. S13813EJ1V0DS00 (1st edition)  
Data Published January 2000 NS CP(K)  
Printed in Japan  
NEC Corporation 1999  
1234567...16

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