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UPD16754N-XXX

更新时间： 2024-09-16 19:46:59
品牌 Logo 应用领域
日电电子 - NEC /
页数 文件大小 规格书
19页 142K
描述
Liquid Crystal Driver, 384-Segment, MOS, TCP

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中文翻译

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UPD16754N-XXX 技术参数

是否Rohs认证： 不符合生命周期：Transferred
零件包装代码：DIE包装说明：DIE,
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.41
数据输入模式：PARALLEL接口集成电路类型：LIQUID CRYSTAL DISPLAY DRIVER
JESD-30 代码：X-XUUC-NJESD-609代码：e0
复用显示功能：NO功能数量：1
区段数：384最高工作温度：75 °C
最低工作温度：-10 °C封装主体材料：UNSPECIFIED
封装代码：DIE封装形状：UNSPECIFIED
封装形式：UNCASED CHIP峰值回流温度（摄氏度）：NOT SPECIFIED
认证状态：Not Qualified最大供电电压：3.6 V
最小供电电压：3 V标称供电电压：3.3 V
电源电压1-最大：9.5 V电源电压1-分钟：8.5 V
电源电压1-Nom：9 V表面贴装：YES
技术：MOS温度等级：COMMERCIAL EXTENDED
端子面层：TIN LEAD端子形式：NO LEAD
端子位置：UPPER处于峰值回流温度下的最长时间：NOT SPECIFIED
最小 fmax：40 MHzBase Number Matches：1

UPD16754N-XXX 数据手册

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DATA SHEET  
MOS INTEGRATED CIRCUIT  
µPD16754  
384-OUTPUT TFT-LCD SOURCE DRIVER  
(COMPATIBLE WITH 256-GRAY SCALES)  
DESCRIPTION  
The µ PD16754 is a source driver for TFT-LCDs capable of dealing with displays with 256-gray scales. Data input  
is based on digital input configured as 8 bits by 6 dots (2 pixels), which can realize a full-color display of 16,777,216  
colors by output of 256 values γ -corrected by an internal D/A converter and 8-by-2 external power modules.  
Because the output dynamic range is as large as VDD2 − 0.2 V to VSS2 + 0.2 V, level inversion operation of the  
LCD’s common electrode is rendered unnecessary. Also, to be able to deal with dot-line inversion, n-line inversion  
and column line inversion when mounted on a single side, this source driver is equipped with a built-in 8-bit D/A  
converter circuit whose odd output pins and even output pins respectively output gray scale voltages of differing  
polarity. Assuring a clock frequency of 40 MHz when driving at 3.0 V, this driver is applicable to XGA-standard TFT-  
LCD panels and SXGA TFT-LCD panels.  
FEATURES  
• CMOS level input  
• 384 Outputs  
• Input of 8 bits (gradation data) by 6 dots  
• Capable of outputting 256 values by means of 8-by-2 external power modules (16 units) and a D/A converter  
• Logic power supply voltage (VDD1): 3.0 to 3.6 V  
• Driver power supply voltage (VDD2): 8.5 to 9.5 V  
• Output dynamic range VDD2 − 0.2 V to VSS2 + 0.2 V  
• High-speed data transfer: fCLK = 40 MHz MAX. (internal data transfer speed when operating at VDD1 = 3.0 V)  
• Apply for dot-line inversion, n-line inversion and column line inversion  
• Output Voltage polarity inversion function (POL)  
• Display data inversion function (POL21, POL22)  
ORDERING INFORMATION  
Part Number  
Package  
µ PD16754N - ×××  
TCP (TAB package)  
Remark The TCP’s external shape is customized. To order the required shape, please contact one of our sales  
representatives.  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all products and/or types are available in every country. Please check with an NEC Electronics  
sales representative for availability and additional information.  
The mark ★ shows major revised points.  
Document No. S16434EJ1V0DS00 (1st edition)  
Date Published April 2003 NS CP(K)  
Printed in Japan  
2001  
1234567...19

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