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UPD16753N-XXX PDF预览

UPD16753N-XXX

更新时间： 2024-11-06 15:56:07
品牌 Logo 应用领域
日电电子 - NEC 驱动接口集成电路
页数 文件大小 规格书
20页 175K
描述
Liquid Crystal Driver, 384-Segment, MOS

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中文翻译

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UPD16753N-XXX 技术参数

生命周期：Obsolete包装说明：DIE,
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.84
数据输入模式：PARALLEL显示模式：DOT MATRIX
接口集成电路类型：LIQUID CRYSTAL DISPLAY DRIVERJESD-30 代码：R-XUUC-N
复用显示功能：NO功能数量：1
区段数：384最高工作温度：75 °C
最低工作温度：-10 °C封装主体材料：UNSPECIFIED
封装代码：DIE封装形状：RECTANGULAR
封装形式：UNCASED CHIP认证状态：Not Qualified
最大供电电压：3.6 V最小供电电压：3 V
标称供电电压：3.3 V电源电压1-最大：9.5 V
电源电压1-分钟：8.5 V电源电压1-Nom：9 V
表面贴装：YES技术：MOS
温度等级：COMMERCIAL EXTENDED端子形式：NO LEAD
端子位置：UPPER最小 fmax：40 MHz
Base Number Matches：1

UPD16753N-XXX 数据手册

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DATA SHEET  
MOS INTEGRATED CIRCUIT  
µ
PD16753  
384-OUTPUT TFT-LCD SOURCE DRIVER  
(COMPATIBLE WITH 256-GRAY SCALES)  
DESCRIPTION  
The µ PD16753 is a source driver for TFT-LCDs capable of dealing with displays with 256-gray scales. Data input  
is based on digital input configured as 8 bits by 6 dots (2 pixels), which can realize a full-color display of 16,777,216  
colors by output of 256 values γ -corrected by an internal D/A converter and 8-by-2 external power modules.  
DD2  
SS2  
Because the output dynamic range is as large as V  
−0.2 V to V  
+0.2 V, level inversion operation of the LCD’s  
common electrode is rendered unnecessary. Also, to be able to deal with dot-line inversion, n-line inversion and  
column line inversion when mounted on a single side, this source driver is equipped with a built-in 8-bit D/A converter  
circuit whose odd output pins and even output pins respectively output gray scale voltages of differing polarity.  
Assuring a clock frequency of 40 MHz when driving at 3.0 V, this driver is applicable to XGA-standard TFT-LCD  
panels and SXGA TFT-LCD panels.  
FEATURES  
• CMOS level input  
• 384 Outputs  
• Input of 8 bits (gradation data) by 6 dots  
• Capable of outputting 256 values by means of 8-by-2 external power modules (16 units) and a D/A converter  
DD1  
• Logic power supply voltage (V ): 3.3 ± 0.3 V  
DD2  
• Driver power supply voltage (V ): 9.0 V ± 0.5 V  
CLK  
DD1  
• High-speed data transfer: f  
= 40 MHz (internal data transfer speed when operating at V  
= 3.0 V)  
DD2  
SS2  
• Output dynamic range V  
−0.2 V to V  
+0.2 V  
• Apply for dot-line inversion, n-line inversion and column line inversion  
• Output Voltage polarity inversion function (POL)  
• Display data inversion function (POL21, POL22)  
• Low power control function (LPC)  
ORDERING INFORMATION  
Part Number  
Package  
µ PD16753N - ×××  
TCP (TAB package)  
Remark The TCP’s external shape is customized. To order the required shape, please contact one of our sales  
representatives.  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all devices/types available in every country. Please check with local NEC representative for  
availability and additional information.  
Document No. S15630EJ1V0DS00 (1st edition)  
Date Published February 2002 NS CP(K)  
Printed in Japan  
The mark ★ shows major revised points.  
2001  
©
1234567...20

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