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UPD16717N-XXX

更新时间： 2024-11-06 19:48:35
品牌 Logo 应用领域
日电电子 - NEC 驱动接口集成电路
页数 文件大小 规格书
20页 196K
描述
Liquid Crystal Driver, 384-Segment, MOS, TCP

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中文翻译

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UPD16717N-XXX 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：DIE包装说明：DIE,
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.92
数据输入模式：PARALLEL显示模式：DOT MATRIX
接口集成电路类型：LIQUID CRYSTAL DISPLAY DRIVERJESD-30 代码：X-XUUC-N
JESD-609代码：e0复用显示功能：NO
功能数量：1区段数：384
最高工作温度：75 °C最低工作温度：-10 °C
封装主体材料：UNSPECIFIED封装代码：DIE
封装形状：UNSPECIFIED封装形式：UNCASED CHIP
峰值回流温度（摄氏度）：NOT SPECIFIED认证状态：Not Qualified
最大供电电压：3.6 V最小供电电压：2.5 V
标称供电电压：3.3 V表面贴装：YES
技术：MOS温度等级：COMMERCIAL EXTENDED
端子面层：TIN LEAD端子形式：NO LEAD
端子位置：UPPER处于峰值回流温度下的最长时间：NOT SPECIFIED
最小 fmax：55 MHzBase Number Matches：1

UPD16717N-XXX 数据手册

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DATA SHEET  
MOS INTEGRATED CIRCUIT  
µPD16717  
384-OUTPUT TFT-LCD SOURCE DRIVER  
(COMPATIBLE WITH 64-GRAY SCALES)  
DESCRIPTION  
The µ PD16717 is a source driver for TFT-LCDs capable of dealing with displays with 64-gray scales. Data input is  
based on digital input configured as 6 bits by 6 dots (2 pixels), which can realize a full-color display of 260,000 colors  
by output of 64 values γ -corrected by an internal D/A converter and 5-by-2 external power modules. Because the  
output dynamic range is as large as VSS2 + 0.2 V to VDD2 – 0.2 V, level inversion operation of the LCD’s common  
electrode is rendered unnecessary. Also, to be able to deal with dot-line inversion, n-line inversion and column line  
inversion when mounted on a single side, this source driver is equipped with a built-in 6-bit D/A converter circuit  
whose odd output pins and even output pins respectively output gray scale voltages of differing polarity. Assuring a  
maximum clock frequency of 55 MHz when driving at 2.5 V, this driver is applicable to XGA-standard TFT-LCD panels  
and SXGA TFT-LCD panels.  
FEATURES  
• CMOS level input (2.5 to 3.6 V)  
• 384 outputs  
• Input of 6 bits (gray-scale data) by 6 dots  
• Capable of outputting 64 values by means of 5-by-2 external power modules (10 units) and a D/A converter (R-DAC)  
• Logic power supply voltage (VDD1): 2.5 to 3.6 V  
• Driver power supply voltage (VDD2): 8.5 V 0.5 V  
• High-speed data transfer: fCLK = 55 MHz (internal data transfer speed when operating at VDD1 = 2.5 V)  
• Output dynamic range: VSS2 + 0.2 V to VDD2 – 0.2 V  
• Apply for dot-line inversion, n-line inversion and column line inversion  
• Output voltage polarity inversion function (POL)  
• Input data inversion function (POL2)  
• Through rate control inversion function (SRC)  
• Output reset control inversion function (MODE)  
• Slim chip  
#
ORDERING INFORMATION  
Part Number  
Package  
µ PD16717N-xxx  
TCP (TAB package)  
Remark The TCP’s external shape is customized. To order the required shape, so please contact one of our  
sales representatives.  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all devices/types available in every country. Please check with local NEC representative for  
availability and additional information.  
Document No. S15375EJ1V0DS00 (1st edition)  
Date Published January 2002 NS CP (K)  
Printed in Japan  
The mark # shows major revised points.  
2001  
©
1234567...20

中文翻译

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