Datasheet > UC3584N

UC3584N

更新时间： 2024-02-28 23:13:09

品牌	Logo	应用领域
德州仪器 - TI		开关光电二极管
页数	文件大小	规格书
7页	155K
描述
Secondary Side Synchronous Post Regulator

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UC3584N 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	DIP
包装说明：	DIP, DIP16,.3	针数：	16
Reach Compliance Code：	not_compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	Factory Lead Time：	1 week
风险等级：	5.66	Is Samacsys：	N
其他特性：	ALSO OPERATES IN CURRENT MODE	模拟集成电路 - 其他类型：	SWITCHING CONTROLLER
控制模式：	VOLTAGE-MODE	控制技术：	PULSE WIDTH MODULATION
最大输入电压：	16 V	最小输入电压：	14 V
标称输入电压：	15 V	JESD-30 代码：	R-PDIP-T16
长度：	19.3 mm	功能数量：	1
端子数量：	16	最高工作温度：	70 °C
最低工作温度：		最大输出电流：	1.5 A
封装主体材料：	PLASTIC/EPOXY	封装代码：	DIP
封装等效代码：	DIP16,.3	封装形状：	RECTANGULAR
封装形式：	IN-LINE	峰值回流温度（摄氏度）：	NOT SPECIFIED
认证状态：	Not Qualified	座面最大高度：	5.33 mm
子类别：	Switching Regulator or Controllers	表面贴装：	NO
切换器配置：	BUCK	最大切换频率：	1000 kHz
温度等级：	COMMERCIAL	端子形式：	THROUGH-HOLE
端子节距：	2.54 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	7.62 mm
Base Number Matches：	1

UC3584N 数据手册

UC1584

UC2584

UC3584

PIN DESCRIPTIONS

BST1: Collector of the boost switch. This is the RT: A Timing Resistor connected between RT and GND

connection point of the external boost inductor and boost sets the discharge current of the timing capacitor.

diode. The boost converter generates the bias supply for

the UC3584 from the regulated 5V output.

SRC: Source connection of the floating driver to the

external switch.

BST2: See BST1. BST2 must be connected externally

SS: Soft Start. An external capacitor is connected

to BST1 pin.

between SS and GND to set the duration of the Soft

CDLY: Delay Set. External CDLY capacitor sets the Start cycle.

delay from the time Short Circuit condition is detected

and Fault Condition is asserted.

SYNC: Synchronization Pin. The UC3584 is

synchronized from the falling edge of the transformer’s

COMP: Output of the Voltage Error Amplifier.

CT: Connect the Timing Capacitor between CT and GND.

FB: Inverting Input of the Voltage Error Amplifier.

GND: Analog System Ground.

secondary winding. Voltage must exceed 1V at minimum

input line.

VCC: Bias supply of the chip, approximately 15V. This is

also the output of the boost regulator. The VCC pin must

be decoupled to PGND.

OUT: Output of the floating driver for an external,

N-channel MOSFET.

VFLT: Positive rail of the floating driver’s bias supply.

Decouple to SRC using a high frequency (ceramic)

capacitor.

PGND: Power Ground. This is the reference node for the

boost bias supply regulator. PGND and GND must be

connected externally.

VREG: Output of the internal 5V regulated supply. Must

be decoupled to GND.

APPLICATION INFORMATION

Biasing the UC3584

Oscillator and Trailing Edge Synchronization

Bias supply for the UC3584 is generated from the main The UC3584 is outfitted with a synchronizable oscillator

output of the power supply by a boost regulator. The in- which also generates a ramp signal across the CT capac-

ductor, diode and capacitor of the boost converter are ex- itor for the PWM comparator. For easy implementation of

ternal components, while the boost switch is internal to the leading edge pulse width modulation technique, the

the chip. The boost converter operates in a burst mode oscillator has an inverted ramp waveform as shown in

with a built-in hysteresis of approximately 1V centered at Fig. 1. The free running oscillator frequency is deter-

15V. This is a bang-bang controller and when enabled mined by the timing components, RT and CT, according

has a fixed duty cycle of 75%.

to the following approximate equations:

1.7

Undervoltage Detection

9.3

R_T

1−D_MAX

The UVLO circuit of the UC3584 monitors the voltage on

VCC. During power up and power down, the pulse width

modulator and the output driver are disabled and OUT is

held active low. Operation is enabled when VCC reaches

10.5V. The UVLO circuitry has a built-in hysteresis of

1.7V (10.5V to 8.8V) thus VCC must drop below 8.8V in

order to assert UVLO again.

2− 8.2×10⁸• C

(

)

f_OSC

0.9

• C_T

(

)

where

R is the timing resistor, its value should be between

Precision Reference

1kΩ and 100kΩ,

An internal precision bandgap reference provides accu-

rate voltages to the error amplifier and other control sec-

tions of the IC. A buffered 5V regulated voltage is also

available for external circuitry on the VREG pin. This pin

must be decoupled to the signal GND connection by a

good quality high frequency capacitor.

C is the timing capacitor,

MAX

is the desired maximum duty cycle, and

is the free running oscillator frequency.

OSC

Figure 2 graphically depicts the measured frequency

data.

1 2 345 6 7

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