TSB41BA3A-EP
IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER
SGLS253B—OCTOBER 2004—REVISED MAY 2011
D Controlled Baseline
D Low-Power Automotive Sleep Mode
− One Assembly/Test Site, One Fabrication
Support
Site
D Fully Compliant With Open Host Controller
D Extended Temperature Performance of
Interface (OHCI) Requirements
−40°C to 110°C
D Cable Power Presence Monitoring
D Enhanced Diminishing Manufacturing
D Cable Ports Monitor Line Conditions for
Sources (DMS) Support
Active Connection to Remote Node
D Enhanced Product-Change Notification
D Register Bits Give Software Control of
Contender Bit, Power Class Bits, Link
Active Control Bit, and 1394a-2000
Features
†
D Qualification Pedigree
D Fully Supports Provisions of IEEE
1394b-2002 at S100, S100B, S200, S200B,
S400, and S400B Signaling Rates
(B Signifies 1394b Signaling)
D Data Interface to Link-Layer Controller
Pin-Selectable From 1394a-2000 Mode
(2/4/8 Parallel Bits at 49.152 MHz) or 1394b
Mode (8 Parallel Bits at 98.304 MHz)
D Fully Supports Provisions of IEEE
1394a-2000 and 1394-1995 Standards for
High-Performance Serial Bus
D Interface to Link-Layer Controller Supports
Low-Cost Texas Instruments Bus-Holder
Isolation
D Fully Interoperable With Firewire™,
DTVLink, SB1394, DishWire, and i.LINK™
Implementation of IEEE Std 1394
D Interoperable With Link-Layer Controllers
Using 3.3-V Supplies
D Provides Three Fully Backward
Compatible, (1394a-2000 Fully Compliant)
Bilingual 1394b Cable Ports at
D Interoperable With Other 1394 Physical
Layers (PHYs) Using 1.8-V, 3.3-V, and 5-V
Supplies
400 Megabits per Second (Mbps)
D Same Three Fully Backward Compatible
Ports Are 1394a-2000 Fully Compliant
Cable Ports at 100/200/400 Mbps
D Low-Cost 49.152-MHz Crystal Provides
Transmit and Receive Data at
100/200/400 Mbps and Link-Layer
Controller Clock at 49.152 MHz and
98.304 MHz
D Full 1394a-2000 Support Includes:
− Connection Debounce
− Arbitrated Short Reset
− Multispeed Concatenation
− Arbitration Acceleration
D Separate Bias (TPBIAS) for Each Port
D Low-Cost, High-Performance, 80-Pin TQFP
(PFP) Thermally Enhanced Package
− Fly-By Concatenation
D Software Device Reset (SWR)
− Port Disable/Suspend/Resume
− Extended Resume Signaling for
Compatibility With Legacy DV Devices
D Fail-Safe Circuitry Senses Sudden Loss of
Power to the Device and Disables the Ports
to Ensure That the TSB41BA3A-EP Does
Not Load the TPBIAS of Any Connected
Device and Blocks Any Leakage From the
Port Back to Power Plane
D Power-Down Features to Conserve Energy
in Battery Powered Applications
†
Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
D 1394a-2000-Compliant Common-Mode
Noise Filter on the Incoming Bias Detect
Circuit to Filter Out Cross-Talk Noise
D Cable/Transceiver Hardware Speed and
Port Mode Are Selectable by Pin States
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Implements technology covered by one or more patents of Apple Computer, Incorporated and SGS Thompson, Limited.
i.LINK is a trademark of Sony Kabushiki Kaisha TA Sony Corporation.
FireWire is a trademark of Apple Computer, Inc. PowerPAD is a trademark of Texas Instruments.
Copyright © 2005 − 2011, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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