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TSB41LV02APAPR PDF预览

TSB41LV02APAPR

更新时间: 2024-11-24 13:14:55
品牌 Logo 应用领域
德州仪器 - TI 线路驱动器或接收器驱动程序和接口
页数 文件大小 规格书
50页 629K
描述
QUAD LINE TRANSCEIVER, PQFP64, PLASTIC, TQFP-64

TSB41LV02APAPR 技术参数

生命周期:Obsolete零件包装代码:QFP
包装说明:TFQFP,针数:64
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.22
差分输出:YES驱动器位数:4
输入特性:DIFFERENTIAL SCHMITT TRIGGER接口集成电路类型:LINE TRANSCEIVER
接口标准:IEEE 1394JESD-30 代码:S-PQFP-G64
长度:10 mm功能数量:4
端子数量:64最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:TFQFP封装形状:SQUARE
封装形式:FLATPACK, THIN PROFILE, FINE PITCH认证状态:Not Qualified
最大接收延迟:接收器位数:4
座面最大高度:1.2 mm最大供电电压:3.6 V
最小供电电压:3 V标称供电电压:3.3 V
表面贴装:YES温度等级:COMMERCIAL
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD最大传输延迟:11 ns
宽度:10 mmBase Number Matches:1

TSB41LV02APAPR 数据手册

 浏览型号TSB41LV02APAPR的Datasheet PDF文件第2页浏览型号TSB41LV02APAPR的Datasheet PDF文件第3页浏览型号TSB41LV02APAPR的Datasheet PDF文件第4页浏览型号TSB41LV02APAPR的Datasheet PDF文件第5页浏览型号TSB41LV02APAPR的Datasheet PDF文件第6页浏览型号TSB41LV02APAPR的Datasheet PDF文件第7页 
TSB41LV02A  
IEEE 1394a TWO PORT CABLE TRANSCEIVER/ARBITER  
SLLS400A – JANUARY 2000 – REVISED MAY 2000  
Fully Supports Provisions of IEEE  
Register Bits Give Software Control of  
1394-1995 Standard for High-Performance  
Serial Bus and the P1394a Supplement  
Contender Bit, Power Class Bits, Link  
Active Control Bit and P1394a Features  
Fully Interoperable With FireWire and  
i.LINK Implementation of IEEE Std 1394  
Data Interface to Link-Layer Controller  
Through 2/4/8 Parallel Lines at 49.152 MHz  
Fully Compliant With OpenHCI  
Requirements  
Interface to Link Layer Controller Supports  
Low Cost TI Bus-holder Isolation and  
Optional Annex J Electrical Isolation  
Provides Two P1394a Fully Compliant  
Cable Ports at 100/200/400 Megabits per  
Second (Mbits/s)  
Interoperable With Link-Layer Controllers  
Using 3.3-V and 5-V Supplies  
Full P1394a Support Includes: Connection  
Debounce, Arbitrated Short Reset,  
Multispeed Concatenation, Arbitration  
Acceleration, Fly-By Concatenation, Port  
Disable/Suspend/Resume  
Interoperable With Other Physical Layers  
(PHYs) Using 3.3-V and 5-V Supplies  
Low Cost 24.576-MHz Crystal Provides  
Transmit, Receive Data at 100/200/400  
Mbits/s, and Link-Layer Controller Clock at  
49.152 MHz  
Extended Resume Signaling for  
Compatibility With Legacy DV Devices  
Incoming Data Resynchronized to Local  
Clock  
Power-Down Features to Conserve Energy  
in Battery Powered Applications Include:  
Automatic Device Power-Down During  
Suspend, Device Power-Down Pin, Link  
Interface Disable via LPS, and Inactive  
Ports Powered Down  
Logic Performs System Initialization and  
Arbitration Functions  
Encode and Decode Functions Included for  
Data-Strobe Bit Level Encoding  
Separate Cable Bias (TPBIAS) for Each Port  
Single 3.3-V Supply Operation  
Ultra Low-Power Sleep Mode  
Node Power Class Information Signaling  
for System Power Management  
Meets Intel Mobile Power Guideline 2000  
Low Cost High Performance 64 Pin TQFP  
(PAP) Thermally Enhanced Package  
Cable Power Presence Monitoring  
Cable Ports Monitor Line Conditions for  
Active Connection to Remote Node  
description  
The TSB41LV02A provides the digital and analog transceiver functions needed to implement a two-port node  
in a cable-based IEEE 1394 network. Each cable port incorporates two differential line transceivers. The  
transceivers include circuitry to monitor the line conditions as needed for determining connection status, for  
initialization and arbitration, and for packet reception and transmission. The TSB41LV02A is designed to  
interface with a link layer controller (LLC), such as the TSB12LV21, TSB12LV22, TSB12LV23, TSB12LV31,  
TSB12LV41, TSB12LV42, or TSB12LV01A.  
The TSB41LV02A requires only an external 24.576 MHz crystal as a reference. An external clock may be  
provided instead of a crystal. An internal oscillator drives an internal phase-locked loop (PLL), which generates  
the required 393.216 MHz reference signal. This reference signal is internally divided to provide the clock  
signals used to control transmission of the outbound encoded strobe and data information. A 49.152 MHz clock  
signal is supplied to the associated LLC for synchronization of the two chips and is used for resynchronization  
of the received data. The power-down (PD) function, when enabled by asserting the PD terminal high, stops  
operation of the PLL.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Implements technology covered by one or more patents of Apple Computer, Incorporated and SGS Thompson, Limited.  
i.LINK is a trademark of Sony Corporation.  
FireWire is a trademark of Apple Computer, Incorporated.  
Copyright 2000, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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