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TSB41AB3_14 PDF预览

TSB41AB3_14

更新时间: 2024-11-21 02:58:51
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
54页 872K
描述
IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER

TSB41AB3_14 数据手册

 浏览型号TSB41AB3_14的Datasheet PDF文件第2页浏览型号TSB41AB3_14的Datasheet PDF文件第3页浏览型号TSB41AB3_14的Datasheet PDF文件第4页浏览型号TSB41AB3_14的Datasheet PDF文件第5页浏览型号TSB41AB3_14的Datasheet PDF文件第6页浏览型号TSB41AB3_14的Datasheet PDF文件第7页 
ꢀꢁ ꢂ ꢃꢄ ꢅꢂ ꢆ  
ꢇ ꢈ ꢈꢈ ꢄ ꢆꢉ ꢃ ꢊ ꢋꢌ ꢍ ꢍ ꢍ ꢀ ꢎꢏꢈꢈ ꢋꢐꢑ ꢏꢀ ꢒꢅꢂ ꢓꢈ ꢀ ꢏꢅꢔꢁ ꢒꢈꢇ ꢕꢈꢏ ꢖꢅ ꢏ ꢂꢇ ꢀ ꢈꢏ  
SLLS418I − JUNE 2000 − REVISED DECEMBER 2004  
D
Fully Supports Provisions of IEEE  
D
D
Data Interface to Link-Layer Controller  
Through 2/4/8 Parallel Lines at 49.152 MHz  
1394-1995 Standard for High Performance  
Serial Bus and the 1394a-2000 Supplement  
Interface to Link Layer Controller Supports  
Low-Cost TI Bus-Holder Isolation and  
Optional Annex J Electrical Isolation  
D
D
D
Fully Interoperable With FireWireand  
i.LINKImplementation of IEEE Std 1394  
Fully Compliant With Open HCI  
Requirements  
D
D
D
Interoperable With Link-Layer Controllers  
Using 3.3-V and 5-V Supplies  
Provides Three 1394a-2000 Fully Compliant  
Cable Ports at 100/200/400 Megabits Per  
Second (Mbits/s)  
Interoperable With Other Physical Layers  
(PHYs) Using 3.3-V and 5-V Supplies  
Low-Cost 24.576-MHz Crystal Provides  
Transmit Receive Data at 100/200/400  
Mbits/s, and Link-Layer Controller Clock at  
49.152 MHz.  
D
Full 1394a-2000 Support Includes:  
Connection Debounce, Arbitrated Short  
Reset, Multispeed Concatenation,  
Arbitration Acceleration, Fly-By  
Concatenation, Port  
D
D
D
D
Separate Cable Bias (TPBIAS) for Each Port  
Single 3.3-V Supply Operation  
Disable/Suspend/Resume  
Low-Cost High Performance 80-Pin TQFP  
(PFP) Thermally Enhanced Package  
D
D
Extended Resume Signaling for  
Compatibility With Legacy DV Devices  
Direct Drop-In Upgrade for  
TSB41LV03APFP and TSB41LV03PFP  
Power-Down Features to Conserve Energy  
in Battery Powered Applications Include:  
Automatic Device Power Down During  
Suspend, Device Power-Down Terminal,  
Link Interface Disable via LPS, and Inactive  
Ports Powered Down  
D
Software Device Reset (SWR)  
D
Fail-Safe Circuitry Senses Sudden Loss of  
Power to the Device and Disables the Ports  
to Ensure That the TSB41AB3 Does Not  
Load the TPBIAS of Any Connected Device  
and Blocks Any Leakage From the Port  
Back to Power Plane.  
D
D
Ultralow-Power Sleep Mode  
Node Power Class Information Signaling  
for System Power Management  
D
The TSB41AB3 Has a 1394a-Compliant  
Common-Mode Noise Filter on the  
Incoming Bias Detect Circuit to Filter Out  
Crosstalk Noise.  
D
Cable Power Presence Monitoring  
D
Cable Ports Monitor Line Conditions for  
Active Connection to Remote Node.  
D
Register Bits Provide Software Control of  
Contender Bit, Power Class Bits, Link  
Active Control Bit and 1394a-2000  
Features.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Implements technology covered by one or more patents of Apple Computer, Incorporated and SGS Thompson, Limited.  
i.LINK is a trademark of Sony Corporation  
FireWire is a trademark of Apple Computer, Incorporated.  
ꢀꢣ  
Copyright 2004, Texas Instruments Incorporated  
ꢟ ꢣ ꢠ ꢟꢙ ꢚꢭ ꢜꢛ ꢊ ꢦꢦ ꢤꢊ ꢝ ꢊ ꢞ ꢣ ꢟ ꢣ ꢝ ꢠ ꢨ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  

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