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TP2104 PDF预览

TP2104

更新时间: 2024-09-28 14:55:31
品牌 Logo 应用领域
美国微芯 - MICROCHIP /
页数 文件大小 规格书
14页 357K
描述
This low threshold, enhancement-mode (normally-off) transistor utilizes a vertical DMOS structure

TP2104 数据手册

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TP2104  
P-Channel Enhancement-Mode Vertical DMOS FET  
Features  
General Description  
• High Input Impedance and High Gain  
• Low-Power Drive Requirement  
• Ease of Paralleling  
The TP2104 low-threshold, Enhancement-mode  
(normally-off) transistor uses a vertical DMOS structure  
and a well-proven silicon-gate manufacturing process.  
This combination produces a device with the power  
handling capabilities of bipolar transistors and the high  
input impedance and positive temperature coefficient  
inherent in MOS devices. Characteristic of all MOS  
structures, this device is free from thermal runaway and  
thermally induced secondary breakdown.  
• Low CISS and Fast Switching Speeds  
• Excellent Thermal Stability  
• Integral Source-Drain Diode  
• Free from Secondary Breakdown  
Applications  
Microchip’s vertical DMOS FETs are ideally suited to a  
wide range of switching and amplifying applications  
where very low threshold voltage, high breakdown  
voltage, high input impedance, low input capacitance  
and fast switching speeds are desired.  
• Logic-Level Interfaces (Ideal for TTL and CMOS)  
• Solid-State Relays  
• Analog Switches  
• Power Management  
Telecommunication Switches  
Package Types  
3-lead SOT-23  
3-lead TO-92  
(Top view)  
(Top view)  
DRAIN  
DRAIN  
SOURCE  
GATE  
SOURCE  
GATE  
See Table 3-1 and Table 3-2 for pin information.  
2020 Microchip Technology Inc.  
DS20005958A-page 1  

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