TMS470R1A384
www.ti.com ......................................................................................................................................................... SPNS110E–AUGUST 2005–REVISED MAY 2008
16/32-Bit RISC Flash Microcontroller
1
FEATURES
23
•
High-Performance Static CMOS Technology
–
Two Serial Communication Interfaces
(SCIs)
•
TMS470R1x 16/32-Bit RISC Core
(ARM7TDMI™)
–
–
224 Selectable Baud Rates
–
–
–
–
24-MHz System Clock (48-MHz Pipeline)
Independent 16/32-Bit Instruction Set
Open Architecture With Third-Party Support
Built-In Debug Module
Asynchronous/Isosynchronous Modes
–
Two Standard CAN Controllers (SCC)
–
–
16-Mailbox Capacity
Fully Compliant With CAN Protocol,
Version 2.0B
•
•
Integrated Memory
–
–
Class II Serial Interface B (C2SIb)
–
384K-Byte Program Flash
–
Normal 10.4 Kbps and 4X Mode
41.6 Kbps
–
Three Banks With 18 Contiguous
Sectors
Three Inter-Integrated Circuit (I2C) Modules
(See I2C Notes in TMS470R1A384 Silicon
Errata, Literature Number SPNZ148)
–
32K-Byte Static RAM (SRAM)
Operating Features
–
–
–
–
Core Supply Voltage (VCC): 1.71 V to 2.05 V
I/O Supply Voltage (VCCIO): 3.0 V to 3.6 V
Low-Power Modes: STANDBY and HALT
Extended Industrial Temperature Range
–
–
–
Multi-Master and Slave Interfaces
Up to 400 Kbps (Fast Mode)
7- and 10-Bit Address Capability
•
High-End Timer (HET)
•
470+ System Module
–
12 Programmable I/O Channels:
12 High-Resolution Pins
–
–
–
–
–
–
32-Bit Address Space Decoding
–
Bus Supervision for Memory/Peripherals
Analog Watchdog (AWD) Timer
–
–
High-Resolution Share Feature (XOR)
High-End Timer RAM
Enhanced Real-Time Interrupt (RTI)
Interrupt Expansion Module (IEM)
System Integrity and Failure Detection
–
64-Instruction Capacity
•
•
External Clock Prescale (ECP) Module
–
Programmable Low-Frequency External
Clock (CLK)
•
•
Direct Memory Access (DMA) Controller
32 Control Packets and 16 Channels
–
12-Channel 10-Bit Multi-Buffered
Analog-to-Digital Converter (MibADC)
Zero-Pin Phase-Locked Loop (ZPLL)-Based
Clock Module With Prescaler
–
–
–
–
32-Word FIFO Buffer
–
–
Multiply-by-4 or -8 Internal ZPLL Option
ZPLL Bypass Mode
Single- or Continuous-Conversion Modes
1.55-µs Minimum Sample/Conversion Time
Calibration Mode and Self-Test Features
•
•
Expansion Bus Module (EBM) (PGE Package)
–
Supports 8- and 16-Bit Expansion Bus
Memory Interface Mappings
•
•
55 Dedicated General-Purpose I/O (GIO) Pins
and 39 Additional Peripheral I/Os (PGE)
–
40 I/O Expansion Bus Pins
14 Dedicated General-Purpose I/O (GIO) Pins
and 39 Additional Peripheral I/Os (PZ)
Ten Communication Interfaces:
Two Serial Peripheral Interfaces (SPIs)
255 Programmable Baud Rates
–
•
•
Flexible Interrupt Handling
Eight External Interrupts
–
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
ARM7TDMI is a trademark of Advanced RISC Machines Limited (ARM).
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2008, Texas Instruments Incorporated