TMS470R1B1M
16/32-Bit RISC Flash Microcontroller
www.ti.com
SPNS109–SEPTEMBER 2005
FEATURES
– Two High-End CAN Controllers (HECC)
•
High-Performance Static CMOS Technology
• 32-Mailbox Capacity
•
TMS470R1x 16/32-Bit RISC Core
(ARM7TDMI™)
• Fully Compliant With CAN Protocol,
Version 2.0B
– 60-MHz System Clock (Pipeline Mode)
– Independent 16/32-Bit Instruction Set
– Open Architecture With Third-Party Support
– Built-In Debug Module
– Five Inter-Integrated Circuit (I2C) Modules
• Multi-Master and Slave Interfaces
• Up to 400 Kbps (Fast Mode)
• 7- and 10-Bit Address Capability
High-End Timer Lite (HET)
•
Integrated Memory
•
– 1M-Byte Program Flash
– 12 Programmable I/O Channels:
• 12 High-Resolution Pins
• Two Banks With 16 Contiguous Sectors
– 64K-Byte Static RAM (SRAM)
– Memory Security Module (MSM)
– JTAG Security Module
– High-Resolution Share Feature (XOR)
– High-End Timer RAM
• 64-Instruction Capacity
•
•
Operating Features
•
•
External Clock Prescale (ECP) Module
– Low-Power Modes: STANDBY and HALT
– Industrial Temperature Range
470+ System Module
– Programmable Low-Frequency External
Clock (CLK)
12-Channel, 10-Bit Multi-Buffered ADC
(MibADC)
– 32-Bit Address Space Decoding
– Bus Supervision for Memory/Peripherals
– Digital Watchdog (DWD) Timer
– Analog Watchdog (AWD) Timer
– Enhanced Real-Time Interrupt (RTI)
– Interrupt Expansion Module (IEM)
– System Integrity and Failure Detection
– ICE Breaker
– 64-Word FIFO Buffer
– Single- or Continuous-Conversion Modes
– 1.55 µs Minimum Sample and Conversion
Time
– Calibration Mode and Self-Test Features
Flexible Interrupt Handling
•
•
Expansion Bus Module (EBM)
– Supports 8- and 16-Bit Expansion Bus
Memory Interface Mappings
•
•
Direct Memory Access (DMA) Controller
– 32 Control Packets and 16 Channels
– 42 I/O Expansion Bus Pins
Zero-Pin Phase-Locked Loop (ZPLL)-Based
Clock Module With Prescaler
•
46 Dedicated General-Purpose I/O (GIO) Pins
and 47 Additional Peripheral I/Os
– Multiply-by-4 or -8 Internal ZPLL Option
– ZPLL Bypass Mode
•
•
Sixteen External Interrupts
On-Chip Scan-Base Emulation Logic, IEEE
Standard 1149.1(1) (JTAG) Test-Access Port
•
Twelve Communication Interfaces:
– Two Serial Peripheral Interfaces (SPIs)
– 255 Programmable Baud Rates
•
144-Pin Plastic Low-Profile Quad Flatpack
(PGE Suffix)
(1)
– Three Serial Communication Interfaces
(SCIs)
• 224 Selectable Baud Rates
The test-access port is compatible with the IEEE Standard
1149.1-1990, IEEE Standard Test-Access Port and Boundary
Scan Architecture specification. Boundary scan is not
supported on this device.
• Asynchronous/Isosynchronous Modes
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
ARM7TDMI is a trademark of Advanced RISC Machines Limited (ARM).
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005, Texas Instruments Incorporated