TMS470R1B768
www.ti.com ......................................................................................................................................................... SPNS108B–AUGUST 2005–REVISED MAY 2008
16/32-Bit RISC Flash Microcontroller
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FEATURES
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Ten Communication Interfaces:
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High-Performance Static CMOS Technology
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Five Serial Peripheral Interfaces (SPIs)
255 Programmable Baud Rates
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TMS470R1x 16/32-Bit RISC Core (ARM7TDM™)
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60-MHz (Pipeline Mode)
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Two Serial Communications Interfaces
(SCIs)
Independent 16/32-Bit Instruction Set
Open Architecture With Third-Party Support
Built-In Debug Module
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224 Selectable Baud Rates
Asynchronous/Isosynchronous Modes
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Three High-End CAN Controllers (HECCs)
Utilizes Big-Endian Format
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32-Mailbox Capacity Each
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Integrated Memory
Fully Compliant With CAN Protocol,
Version 2.0B
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768K-Byte Program Flash
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3 Banks With 18 Contiguous Sectors
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High-End Timer (HET)
Internal State Machine for Programming
and Erase
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32 Programmable I/O Channels:
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24 High-Resolution Pins
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48K-Byte Static RAM (SRAM)
8 Standard-Resolution Pins
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15 Dedicated GIO Pins, 1 Input-Only GIO Pin,
and 71 Additional Peripheral I/Os
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High-Resolution Share Feature (XOR)
High-End Timer RAM
Operating Features
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Core Supply Voltage (VCC): 1.81–2.05 V
I/O Supply Voltage (VCCIO): 3.0–3.6 V
Low-Power Modes: STANDBY and HALT
Extended Industrial Temperature Range
– 128-Instruction Capacity
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16-Channel 10-Bit Multi-Buffered ADC
(MibADC)
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256-Word FIFO Buffer
Single- or Continuous-Conversion Modes
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470+ System Module
1.55-µs Minimum Sample and Conversion
Time
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32-Bit Address Space Decoding
Bus Supervision for Memory and
Peripherals
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Calibration Mode and Self-Test Features
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Eight External Interrupts
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Analog Watchdog (AWD) Timer
Real-Time Interrupt (RTI)
Flexible Interrupt Handling
External Clock Prescale (ECP) Module
System Integrity and Failure Detection
Interrupt Expansion Module (IEM)
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Programmable Low-Frequency External
Clock (CLK)
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Direct Memory Access (DMA) Controller
32 Control Packets and 16 Channels
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On-Chip Scan-Base Emulation Logic, IEEE
Standard 1149.1(1) (JTAG) Test-Access Port
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Zero-Pin Phase-Locked Loop (ZPLL)-Based
Clock Module With Prescaler
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144-Pin Plastic Low-Profile Quad Flatpack
(PGE Suffix)
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Multiply-by-4 or -8 Internal ZPLL Option
ZPLL Bypass Mode
(1)
The test-access port is compatible with the IEEE Standard
1149.1-1990, IEEE Standard Test-Access Port and Boundary
Scan Architecture specification. Boundary scan is not
supported on this device.
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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ARM7TDM is a trademark of Advanced RISC Machines Limited (ARM).
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2008, Texas Instruments Incorporated