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TMS470R1B768_08 PDF预览

TMS470R1B768_08

更新时间: 2024-09-24 04:27:51
品牌 Logo 应用领域
德州仪器 - TI 闪存微控制器
页数 文件大小 规格书
49页 534K
描述
16/32-Bit RISC Flash Microcontroller

TMS470R1B768_08 数据手册

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TMS470R1B768  
www.ti.com ......................................................................................................................................................... SPNS108BAUGUST 2005REVISED MAY 2008  
16/32-Bit RISC Flash Microcontroller  
1
FEATURES  
Ten Communication Interfaces:  
23  
High-Performance Static CMOS Technology  
Five Serial Peripheral Interfaces (SPIs)  
255 Programmable Baud Rates  
TMS470R1x 16/32-Bit RISC Core (ARM7TDM™)  
60-MHz (Pipeline Mode)  
Two Serial Communications Interfaces  
(SCIs)  
Independent 16/32-Bit Instruction Set  
Open Architecture With Third-Party Support  
Built-In Debug Module  
224 Selectable Baud Rates  
Asynchronous/Isosynchronous Modes  
Three High-End CAN Controllers (HECCs)  
Utilizes Big-Endian Format  
32-Mailbox Capacity Each  
Integrated Memory  
Fully Compliant With CAN Protocol,  
Version 2.0B  
768K-Byte Program Flash  
3 Banks With 18 Contiguous Sectors  
High-End Timer (HET)  
Internal State Machine for Programming  
and Erase  
32 Programmable I/O Channels:  
24 High-Resolution Pins  
48K-Byte Static RAM (SRAM)  
8 Standard-Resolution Pins  
15 Dedicated GIO Pins, 1 Input-Only GIO Pin,  
and 71 Additional Peripheral I/Os  
High-Resolution Share Feature (XOR)  
High-End Timer RAM  
Operating Features  
Core Supply Voltage (VCC): 1.81–2.05 V  
I/O Supply Voltage (VCCIO): 3.0–3.6 V  
Low-Power Modes: STANDBY and HALT  
Extended Industrial Temperature Range  
– 128-Instruction Capacity  
16-Channel 10-Bit Multi-Buffered ADC  
(MibADC)  
256-Word FIFO Buffer  
Single- or Continuous-Conversion Modes  
470+ System Module  
1.55-µs Minimum Sample and Conversion  
Time  
32-Bit Address Space Decoding  
Bus Supervision for Memory and  
Peripherals  
Calibration Mode and Self-Test Features  
Eight External Interrupts  
Analog Watchdog (AWD) Timer  
Real-Time Interrupt (RTI)  
Flexible Interrupt Handling  
External Clock Prescale (ECP) Module  
System Integrity and Failure Detection  
Interrupt Expansion Module (IEM)  
Programmable Low-Frequency External  
Clock (CLK)  
Direct Memory Access (DMA) Controller  
32 Control Packets and 16 Channels  
On-Chip Scan-Base Emulation Logic, IEEE  
Standard 1149.1(1) (JTAG) Test-Access Port  
Zero-Pin Phase-Locked Loop (ZPLL)-Based  
Clock Module With Prescaler  
144-Pin Plastic Low-Profile Quad Flatpack  
(PGE Suffix)  
Multiply-by-4 or -8 Internal ZPLL Option  
ZPLL Bypass Mode  
(1)  
The test-access port is compatible with the IEEE Standard  
1149.1-1990, IEEE Standard Test-Access Port and Boundary  
Scan Architecture specification. Boundary scan is not  
supported on this device.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
3
ARM7TDM is a trademark of Advanced RISC Machines Limited (ARM).  
All other trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2005–2008, Texas Instruments Incorporated  

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