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TMS470R1B512PGEQ PDF预览

TMS470R1B512PGEQ

更新时间: 2024-09-24 12:58:31
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德州仪器 - TI 闪存微控制器
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46页 433K
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TMS470R1B512PGEQ 数据手册

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TMS470R1B512  
16/32-Bit RISC Flash Microcontroller  
www.ti.com  
SPNS107SEPTEMBER 2005  
FEATURES  
External Clock Prescale (ECP) Module  
High-Performance Static CMOS Technology  
– Programmable Low-Frequency External  
Clock (CLK)  
TMS470R1x 16/32-Bit RISC Core  
(ARM7TDMI™)  
Seven Communication Interfaces:  
– Three Serial Peripheral Interfaces (SPIs)  
255 Programmable Baud Rates  
– 24-MHz System Clock (60-MHz Pipeline  
Mode)  
– Independent 16/32-Bit Instruction Set  
– Open Architecture With Third-Party Support  
– Built-In Debug Module  
– Two Serial Communications Interfaces  
(SCIs)  
224 Selectable Baud Rates  
– Utilizes Big-Endian Format  
Asynchronous/Isosynchronous Modes  
Two High-End CAN Controllers (HECCs)  
32-Mailbox Capacity Each  
Integrated Memory  
– 512K-Byte Program Flash  
2 Banks With 14 Contiguous Sectors  
Fully Compliant With CAN Protocol,  
Version 2.0B  
Internal State Machine for Programming  
and Erase  
High-End Timer (HET)  
– 32K-Byte Static RAM (SRAM)  
– 32 Programmable I/O Channels:  
24 High-Resolution Pins  
8 Standard-Resolution Pins  
– High-Resolution Share Feature (XOR)  
– High-End Timer RAM  
27 Dedicated GIO Pins, 1 Input-Only GIO Pin,  
and 59 Additional Peripheral I/Os  
Operating Features  
– Core Supply Voltage (V CC ): 1.81 V – 2.05 V  
– I/O Supply Voltage (VCCIO): 3.0 V – 3.6 V  
– Low-Power Modes: STANDBY and HALT  
– Extended Industrial Temperature Range  
470+ System Module  
128-Instruction Capacity  
16-Channel 10-Bit Multi-Buffered ADC  
(MibADC)  
– 128-Word FIFO Buffer  
– 32-Bit Address Space Decoding  
– Single- or Continuous-Conversion Modes  
– Bus Supervision for Memory and  
Peripherals  
– 1.55 µs Minimum Sample and Conversion  
Time  
– Analog Watchdog (AWD) Timer  
– Real-Time Interrupt (RTI)  
– Calibration Mode and Self-Test Features  
Eight External Interrupts  
– System Integrity and Failure Detection  
– Interrupt Expansion Module (IEM)  
Direct Memory Access (DMA) Controller  
– 32 Control Packets and 16 Channels  
Flexible Interrupt Handling  
On-Chip Scan-Base Emulation Logic, IEEE  
Standard 1149.1(1) (JTAG) Test-Access Port  
144-Pin Plastic Low-Profile Quad Flatpack  
(PGE Suffix)  
Zero-Pin Phase-Locked Loop (ZPLL)-Based  
Clock Module With Prescaler  
(1)  
The test-access port is compatible with the IEEE Standard  
1149.1-1990, IEEE Standard Test-Access Port and Boundary  
Scan Architecture specification. Boundary scan is not  
– Multiply-by-4 or -8 Internal ZPLL Option  
– ZPLL Bypass Mode  
supported on this device.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ARM7TDMI is a trademark of Advanced RISC Machines Limited (ARM).  
All trademarks are the property of their respective owners.  
ADVANCE INFORMATION concerns new products in the sampling  
or preproduction phase of development. Characteristic data and  
other specifications are subject to change without notice.  
Copyright © 2005, Texas Instruments Incorporated  

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