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TMS470R1A64 PDF预览

TMS470R1A64

更新时间： 2024-09-23 21:55:31
品牌 Logo 应用领域
德州仪器 - TI 闪存微控制器
页数 文件大小 规格书
46页 366K
描述
16/32-Bit RISC Flash Microcontroller

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TMS470R1A64 数据手册

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TMS470R1A64  
16/32-Bit RISC Flash Microcontroller  
www.ti.com  
SPNS099–NOVEMBER 2004  
•
•
High-Performance Static CMOS Technology  
• Asynchronous/Isosynchronous Modes  
– Standard CAN Controller (SCC)  
– 16-Mailbox Capacity  
TMS470R1x 16/32-Bit RISC Core  
(ARM7TDMI™)  
– 24-MHz System Clock (48-MHz Pipeline  
Mode)  
• Fully Compliant With CAN Protocol, Version  
2.0B  
– Independent 16/32-Bit Instruction Set  
– Open Architecture With Third-Party Support  
– Built-In Debug Module  
– Class II Serial Interface (C2SIa)  
• Two Selectable Data Rates  
• Normal Mode 10.4 Kbps and 4X Mode 41.6  
– Big-Endian Format Utilized  
Kbps  
•
Integrated Memory  
•
•
High-End Timer (HET)  
– 64K-Byte Program Flash  
– 13 Programmable I/O Channels:  
• 12 High-Resolution Pins  
• One Bank With Five Contiguous Sectors  
• Internal State Machine for Programming  
and Erase  
• 1 Standard-Resolution Pin  
– High-Resolution Share Feature (XOR)  
– HET RAM (64-Instruction Capacity)  
– 4K-Byte Static RAM (SRAM)  
•
•
Operating Features  
10-Bit Multi-Buffered ADC (MibADC)  
8-Channel  
– Core Supply Voltage (VCC): 1.71 V–2.05 V  
– I/O Supply Voltage (VCCIO): 3.0 V–3.6 V  
– Low-Power Modes: STANDBY and HALT  
– Industrial Temperature Ranges  
470+ System Module  
– 64-Word FIFO Buffer  
– Single- or Continuous-Conversion Modes  
– 1.55 µs Minimum Sample and Conversion  
Time  
– Calibration Mode and Self-Test Features  
Six External Interrupts  
– 32-Bit Address Space Decoding  
•
•
•
– Bus Supervision for Memory and  
Peripherals  
Flexible Interrupt Handling  
– Analog Watchdog (AWD) Timer  
– Real-Time Interrupt (RTI)  
5 Dedicated General-Purpose I/O (GIO) Pins, 1  
Input-Only GIO Pin, and 34 Additional  
Peripheral I/Os  
– System Integrity and Failure Detection  
•
External Clock Prescale (ECP) Module  
•
•
Zero-Pin Phase-Locked Loop (ZPLL)-Based  
Clock Module With Prescaler  
– Programmable Low-Frequency External  
Clock (CLK)  
– Multiply-by-4 or -8 Internal ZPLL Option  
– ZPLL Bypass Mode  
•
•
On-Chip Scan-Base Emulation Logic, IEEE  
Standard 1149.1 (1) (JTAG) Test-Access Port  
Six Communication Interfaces:  
80-Pin Plastic Low-Profile Quad Flatpack (PN  
Suffix)  
– Two Serial Peripheral Interfaces (SPIs)  
• 255 Programmable Baud Rates  
– Two Serial Communication Interfaces (SCIs)  
• 224 Selectable Baud Rates  
(1) The test-access port is compatible with the IEEE Standard  
1149.1-1990, IEEE Standard Test-Access Port and Boundary  
Scan Architecture specification. Boundary scan is not sup-  
ported on this device.  
ARM7TDMI is a trademark of Advanced RISC Machines (ARM) Limited.  
ADVANCE INFORMATION concerns new products in the sampling  
or preproduction phase of development. Characteristic data and  
other specifications are subject to change without notice.  
Copyright © 2004, Texas Instruments Incorporated  
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