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TMS470R1A288PZA PDF预览

TMS470R1A288PZA

更新时间： 2024-11-12 13:14:51
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德州仪器 - TI 闪存微控制器
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TMS470R1A288  
16/32-Bit RISC Flash Microcontroller  
www.ti.com  
SPNS106–SEPTEMBER 2005  
FEATURES  
• 16-Mailbox Capacity  
•
High-Performance Static CMOS Technology  
• Fully Compliant With CAN Protocol,  
Version 2.0B  
•
TMS470R1x 16/32-Bit RISC Core  
(ARM7TDMI™)  
– Three Inter-Integrated Circuit (I2C) Modules  
• Multi-Master and Slave Interfaces  
• Up to 400 Kbps (Fast Mode)  
• 7- and 10-Bit Address Capability  
High-End Timer Lite (HET)  
– 24-MHz System Clock (48-MHz Pipeline)  
– Independent 16/32-Bit Instruction Set  
– Open Architecture With Third-Party Support  
– Built-In Debug Module  
•
•
Integrated Memory  
– 12 Programmable I/O Channels:  
• 12 High-Resolution Pins  
– 288K-Byte Program Flash  
• Two Banks With 8 Contiguous Sectors  
– 16K-Byte Static RAM (SRAM)  
– Memory Security Module (MSM)  
– JTAG Security Module  
– High-Resolution Share Feature (XOR)  
– High-End Timer RAM  
• 64-Instruction Capacity  
•
•
External Clock Prescale (ECP) Module  
•
•
Operating Features  
– Programmable Low-Frequency External  
Clock (CLK)  
– Low-Power Modes: STANDBY and HALT  
– Industrial Temperature Range  
470+ System Module  
12-Channel 10-Bit Multi-Buffered ADC  
(MibADC)  
– 64-Word FIFO Buffer  
– 32-Bit Address Space Decoding  
– Bus Supervision for Memory/Peripherals  
– Digital Watchdog (DWD) Timer  
– Analog Watchdog (AWD) Timer  
– Enhanced Real-Time Interrupt (RTI)  
– Interrupt Expansion Module (IEM)  
– System Integrity and Failure Detection  
– ICE Breaker  
– Single- or Continuous-Conversion Modes  
– 1.55 µs Minimum Sample/Conversion Time  
– Calibration Mode and Self-Test Features  
Flexible Interrupt Handling  
•
•
Expansion Bus Module (EBM) (PGE only)  
– Supports 8- and 16-Bit Expansion Bus  
Memory Interface Mappings  
– 42 I/O Expansion Bus Pins  
•
•
Direct Memory Access (DMA) Controller  
– 32 Control Packets and 16 Channels  
•
•
50 Dedicated General-Purpose I/O (GIO) Pins  
and 43 Additional Peripheral I/Os (PGE)  
Zero-Pin Phase-Locked Loop (ZPLL)-Based  
Clock Module With Prescaler  
14 Dedicated General-Purpose I/O (GIO) Pins  
and 43 Additional Peripheral I/Os (PZ)  
– Multiply-by-8 Internal ZPLL Option  
– ZPLL Bypass Mode  
•
•
16 External Interrupts  
On-Chip Scan-Base Emulation Logic, IEEE  
Standard 1149.1(1) (JTAG) Test-Access Port  
•
Ten Communication Interfaces:  
– Two Serial Peripheral Interfaces (SPIs)  
• 255 Programmable Baud Rates  
– Two Serial Communication Interfaces (SCIs)  
• 224 Selectable Baud Rates  
•
144-Pin Plastic Low-Profile Quad Flatpack  
(PGE Suffix)  
•
100-Pin Plastic Low-Profile Quad Flatpack (PZ  
Suffix)  
(1)  
The test-access port is compatible with the IEEE Standard  
1149.1-1990, IEEE Standard Test-Access Port and Boundary  
Scan Architecture specification. Boundary scan is not  
• Asynchronous/Isosynchronous Modes  
– Class II Serial Interface B (C2SIb)  
• Normal 10.4 Kbps and 4X Mode 41.6 Kbps  
– Two Standard CAN Controllers (SCC)  
supported on this device.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ARM7TDMI is a trademark of Advanced RISC Machines Limited (ARM).  
All trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2005, Texas Instruments Incorporated  
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