TMS470R1A288
16/32-Bit RISC Flash Microcontroller
www.ti.com
SPNS106B–SEPTEMBER 2005–REVISED AUGUST 2006
FEATURES
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Two Serial Peripheral Interfaces (SPIs)
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High-Performance Static CMOS Technology
– 255 Programmable Baud Rates
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TMS470R1x 16/32-Bit RISC Core
(ARM7TDMI™)
Two Serial Communication Interfaces
(SCIs)
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24-MHz System Clock (48-MHz Pipeline)
Independent 16/32-Bit Instruction Set
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224 Selectable Baud Rates
Asynchronous/Isosynchronous Modes
Open Architecture With Third-Party
Support
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Class II Serial Interface B (C2SIb)
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Normal 10.4 Kbps and 4X Mode 41.6
Kbps
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Built-In Debug Module
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Integrated Memory
Two Standard CAN Controllers (SCC)
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288K-Byte Program Flash
Two Banks With 8 Contiguous Sectors
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16-Mailbox Capacity
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Fully Compliant With CAN Protocol,
Version 2.0B
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16K-Byte Static RAM (SRAM)
Memory Security Module (MSM)
JTAG Security Module
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Three Inter-Integrated Circuit (I2C) Modules
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Multi-Master and Slave Interfaces
Up to 400 Kbps (Fast Mode)
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Operating Features
7- and 10-Bit Address Capability
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Low-Power Modes: STANDBY and HALT
Extended Industrial Temperature Range
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12-Channel 10-Bit Multi-Buffered ADC
(MibADC)
470+ System Module
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64-Word FIFO Buffer
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32-Bit Address Space Decoding
Bus Supervision for Memory/Peripherals
Digital Watchdog (DWD) Timer
Analog Watchdog (AWD) Timer
Enhanced Real-Time Interrupt (RTI)
Interrupt Expansion Module (IEM)
System Integrity and Failure Detection
ICE Breaker
Single- or Continuous-Conversion Modes
1.55 µs Minimum Sample/Conversion Time
Calibration Mode and Self-Test Features
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Flexible Interrupt Handling
Expansion Bus Module (EBM) (PGE only)
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Supports 8- and 16-Bit Expansion Bus
Memory Interface Mappings
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42 I/O Expansion Bus Pins
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Direct Memory Access (DMA) Controller
32 Control Packets and 16 Channels
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50 Dedicated General-Purpose I/O (GIO) Pins
and 43 Additional Peripheral I/Os (PGE)
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Zero-Pin Phase-Locked Loop (ZPLL)-Based
Clock Module With Prescaler
14 Dedicated General-Purpose I/O (GIO) Pins
and 43 Additional Peripheral I/Os (PZ)
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Multiply-by-8 Internal ZPLL Option
ZPLL Bypass Mode
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16 External Interrupts
On-Chip Scan-Base Emulation Logic, IEEE
Standard 1149.1(1) (JTAG) Test-Access Port
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High-End Timer Lite (HET)
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12 Programmable I/O Channels:
12 High-Resolution Pins
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144-Pin Plastic Low-Profile Quad Flatpack
(PGE Suffix)
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High-Resolution Share Feature (XOR)
High-End Timer RAM
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100-Pin Plastic Low-Profile Quad Flatpack (PZ
Suffix)
(1)
The test-access port is compatible with the IEEE Standard
1149.1-1990, IEEE Standard Test-Access Port and Boundary
Scan Architecture specification. Boundary scan is not
supported on this device.
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64-Instruction Capacity
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External Clock Prescale (ECP) Module
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Programmable Low-Frequency External
Clock (CLK)
Ten Communication Interfaces:
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
ARM7TDMI is a trademark of Advanced RISC Machines Limited (ARM).
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2006, Texas Instruments Incorporated