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SMHS160D − AUGUST 1992 − REVISED JUNE 1995
DZ PACKAGE
(TOP VIEW)
DGE PACKAGE
(TOP VIEW)
This data sheet is applicable to all TMS45160/Ps
symbolized with Revision “D” and subsequent
revisions as described on page 21.
1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
1
2
3
4
5
6
7
8
9
10
44
43
42
41
40
39
38
37
36
35
V
V
V
V
SS
CC
SS
CC
2
3
4
5
6
7
8
9
DQ0
DQ1
DQ2
DQ3
DQ15
DQ14
DQ13
DQ12
DQ0
DQ1
DQ2
DQ3
DQ15
DQ14
DQ13
DQ12
D Organization . . . 262144 × 16
D 5-V Supply ( 10% Tolerance)
D Performance Ranges:
V
V
V
V
ACCESS ACCESS ACCESS READ OR
CC
SS
CC
SS
TIME
TIME
TIME
WRITE
CYCLE
MIN
DQ4
DQ5
DQ6
DQ7
NC
NC
W
RAS
NC
A0
DQ11
DQ10
DQ9
DQ8
NC
LCAS
UCAS
OE
A8
A7
A6
A5
DQ4
DQ5
DQ6
DQ7
DQ11
DQ10
DQ9
t
t
t
RAC
CAC
AA
MAX
MAX
MAX
’45160/P-60
’45160/P-70
’45160/P-80
60 ns
70 ns
80 ns
15 ns
20 ns
20 ns
30 ns
35 ns
40 ns
110 ns
130 ns
150 ns
10
11
12
13
14
15
16
17
18
19
20
DQ8
D Enhanced-Page-Mode Operation With
13
32
NC
NC
NC 14
31 LCAS
xCAS-Before-RAS (xCBR) Refresh
15
16
17
18
19
20
21
22
30
29
28
27
26
25
24
23
W
RAS
NC
A0
UCAS
OE
A8
A7
A6
D Long Refresh Period
512-Cycle Refresh in 8 ms (Max)
64 ms Max for Low Power With
Self-Refresh Version (TMS45160P)
A1
A2
A3
A1
A2
A3
A4
V
A5
A4
V
D 3-State Unlatched Output
CC
SS
D Low Power Dissipation
V
V
CC
SS
D Texas Instruments EPIC CMOS Process
D All Inputs, Outputs, and Clocks Are TTL
Compatible
PIN NOMENCLATURE
D High-Reliability, 40-Lead, 400-Mil-Wide
Plastic Surface-Mount (SOJ) Package and
40/44-Lead Thin Small-Outline Package
(TSOP)
A0−A8
Address Inputs
Data In/Data Out
DQ0−DQ15
LCAS
NC
OE
RAS
Lower Column-Address Strobe
No Internal Connection
Output Enable
Row-Address Strobe
Upper Column-Address Strobe
5-V Supply
D Operating Free-Air Temperature Range
0°C to 70°C
UCAS
D Low Power With Self-Refresh Version
V
CC
V
SS
D Upper and Lower Byte Control During Read
Ground
Write Enable
W
and Write Operations
description
The TMS45160 series are high-speed, 4194304-bit dynamic random-access memories organized as 262144
words of 16 bits each. The TMS45160P series are high-speed, low-power, self-refresh 4194304-bit dynamic
random-access memories organized as 262144 words of 16 bits each. They employ state-of-the-art EPIC
(Enhanced Performance Implanted CMOS) technology for high performance, reliability, and low power at low
cost.
These devices feature maximum RAS access times of 60 ns, 70 ns, and 80 ns. Maximum power dissipation
is as low as 770 mW operating and 11 mW standby on 80-ns devices. All inputs and outputs, including clocks,
are compatible with Series 74 TTL. All addresses and data-in lines are latched on chip to simplify system design.
Data out is unlatched to allow greater system flexibility.
The TMS45160 and TMS45160P are each offered in a 40-lead plastic surface-mount SOJ package (DZ suffix)
and a 40/44-lead plastic surface-mount small-outline (TSOP) package (DGE suffix). These packages are
characterized for operation from 0°C to 70°C.
EPIC is a trademark of Texas Instruments Incorporated.
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Copyright 1995, Texas Instruments Incorporated
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ꢢ ꢦ ꢣ ꢢꢛ ꢜꢰ ꢞꢝ ꢡ ꢩꢩ ꢧꢡ ꢟ ꢡ ꢠ ꢦ ꢢ ꢦ ꢟ ꢣ ꢫ
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1
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