TL16C550D, TL16C550DI
www.ti.com .................................................................................................................................................. SLLS597E–APRIL 2004–REVISED DECEMBER 2008
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH AUTOFLOW CONTROL
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FEATURES
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Programmable Auto-RTS and Auto-CTS
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Standard Asynchronous Communication Bits
(Start, Stop, and Parity) Added to or Deleted
From the Serial Data Stream
In Auto-CTS Mode, CTS Controls Transmitter
In Auto-RTS Mode, RCV FIFO Contents and
Threshold Control RTS
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5-V, 3.3-V, and 2.5-V Operation
Independent Receiver Clock Input
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Serial and Modem Control Outputs Drive a
RJ11 Cable Directly When Equipment Is on the
Same Power Drop
Transmit, Receive, Line Status, and Data Set
Interrupts Independently Controlled
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Capable of Running With All Existing
TL16C450 Software
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Fully Programmable Serial Interface
Characteristics:
After Reset, All Registers Are Identical to the
TL16C450 Register Set
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5-, 6-, 7-, or 8-Bit Characters
Even-, Odd-, or No-Parity Bit Generation
and Detection
Up to 24-MHz Clock Rate for up to 1.5-Mbaud
Operation With VCC = 5 V
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1-, 1 =-, or 2-Stop Bit Generation
Up to 20-MHz Clock Rate for up to 1.25-Mbaud
Operation With VCC = 3.3 V
Baud Generation (dc to 1 Mbit/s)
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False-Start Bit Detection
Up to 48-MHz Clock Rate for up to 3-Mbaud
Operation with VCC = 3.3 V (ZQS Package Only,
Divisor = 1)
Complete Status Reporting Capabilities
3-State Output TTL Drive Capabilities for
Bidirectional Data Bus and Control Bus
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Up to 40-MHz Clock Rate for up to 2.5-Mbaud
Operation with VCC = 3.3 V (ZQS Package Only,
Divisor ≥ 2)
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Line Break Generation and Detection
Internal Diagnostic Capabilities:
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Loopback Controls for Communications
Link Fault Isolation
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Up to 16-MHz Clock Rate for up to 1-Mbaud
Operation With VCC = 2.5 V
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Break, Parity, Overrun, and Framing Error
Simulation
In the TL16C450 Mode, Hold and Shift
Registers Eliminate the Need for Precise
Synchronization Between the CPU and Serial
Data
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Fully Prioritized Interrupt System Controls
Modem Control Functions (CTS, RTS, DSR,
DTR, RI, and DCD)
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Programmable Baud Rate Generator Allows
Division of Any Input Reference Clock by 1 to
(216 –1) and Generates an Internal 16× Clock
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Available in 48-Pin PT, 48-Pin PFB, 32-Pin
RHB, and 24-Pin ZQS Packages
DESCRIPTION/ORDERING INFORMATION
The TL16C550D and the TL16C550DI are speed and operating voltage upgrades (but functional equivalents) of
the TL16C550C asynchronous communications element (ACE), which in turn is a functional upgrade of the
TL16C450. Functionally equivalent to the TL16C450 on power up (character or TL16C450 mode), the
TL16C550D and the TL16C550DI, like the TL16C550C, can be placed in an alternate FIFO mode. This relieves
the CPU of excessive software overhead by buffering received and transmitted characters. The receiver and
transmitter FIFOs store up to 16 bytes including three additional bits of error status per byte for the receiver
FIFO. In the FIFO mode, there is a selectable autoflow control feature that can significantly reduce software
overload and increase system efficiency by automatically controlling serial data flow using RTS output and CTS
input signals.
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2004–2008, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.