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SLLS597C − APRIL 2004 − REVISED JUNE 2005
D
D
D
D
Programmable Auto-RTS and Auto-CTS
D
D
D
D
5-V, 3.3-V, and 2.5-V Operation
In Auto-CTS Mode, CTS Controls
Transmitter
Independent Receiver Clock Input
Transmit, Receive, Line Status, and Data
Set Interrupts Independently Controlled
In Auto-RTS Mode, RCV FIFO Contents and
Threshold Control RTS
Fully Programmable Serial Interface
Characteristics:
− 5-, 6-, 7-, or 8-Bit Characters
− Even-, Odd-, or No-Parity Bit Generation
and Detection
Serial and Modem Control Outputs Drive a
RJ11 Cable Directly When Equipment Is on
the Same Power Drop
D
D
D
D
D
D
Capable of Running With All Existing
TL16C450 Software
− 1-, 1 1/2-, or 2-Stop Bit Generation
− Baud Generation (dc to 1 Mbit/s)
After Reset, All Registers Are Identical to
the TL16C450 Register Set
D
D
D
False-Start Bit Detection
Complete Status Reporting Capabilities
Up to 24-MHz Clock Rate for up to
1.5-Mbaud Operation With V = 5 V
3-State Output TTL Drive Capabilities for
Bidirectional Data Bus and Control Bus
CC
Up to 20-MHz Clock Rate for up to
1.25-Mbaud Operation With V = 3.3 V
D
Line Break Generation and Detection
CC
Up to 16-MHz Clock Rate for up to 1-Mbaud
D
Internal Diagnostic Capabilities:
− Loopback Controls for Communications
Link Fault Isolation
− Break, Parity, Overrun, and Framing
Error Simulation
Operation With V = 2.5 V
CC
In the TL16C450 Mode, Hold and Shift
Registers Eliminate the Need for Precise
Synchronization Between the CPU and
Serial Data
D
D
D
Fully Prioritized Interrupt System Controls
D
D
Programmable Baud Rate Generator Allows
Division of Any Input Reference Clock by 1
Modem Control Functions (CTS, RTS, DSR,
DTR, RI, and DCD)
16
to (2 −1) and Generates an Internal 16×
Available in 48-Pin PT, 48-Pin PFB, and
32-Pin RHB Packages
Clock
Standard Asynchronous Communication
Bits (Start, Stop, and Parity) Added to or
Deleted From the Serial Data Stream
description
The TL16C550D and the TL16C550DI are speed and operating voltage upgrades (but functional equivalents)
of the TL16C550C asynchronous communications element (ACE), which in turn is a functional upgrade of the
TL16C450. Functionally equivalent to the TL16C450 on power up (character or TL16C450 mode), the
TL16C550D and the TL16C550DI, like the TL16C550C, can be placed in an alternate FIFO mode. This relieves
the CPU of excessive software overhead by buffering received and transmitted characters. The receiver and
transmitter FIFOs store up to 16 bytes including three additional bits of error status per byte for the receiver
FIFO. In the FIFO mode, there is a selectable autoflow control feature that can significantly reduce software
overload and increase system efficiency by automatically controlling serial data flow using RTS output and CTS
input signals.
The TL16C550D and TL16C550DI perform serial-to-parallel conversions on data received from a peripheral
device or modem and parallel-to-serial conversion on data received from its CPU. The CPU can read the ACE
status at any time. The ACE includes complete modem control capability and a processor interrupt system that
can be tailored to minimize software management of the communications link.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2004 − 2005, Texas Instruments Incorporated
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1
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