TL16C2752
www.ti.com ................................................................................................................................................ SLWS188A–JUNE 2006–REVISED SEPTEMBER 2008
1.8-V to 5-V DUAL UART WITH 64-BYTE FIFOS
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FEATURES
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Larger FIFOs Reduce CPU Overhead
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Fully Programmable Serial Interface
Characteristics
Programmable Auto-RTS and Auto-CTS
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5-, 6-, 7-, or 8-Bit Characters
In Auto-CTS Mode, CTS Controls the
Transmitter
Even-, Odd-, or No-Parity Bit Generation
and Detection
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In Auto-RTS Mode, RCV FIFO Contents, and
Threshold Control RTS
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1-, 1 =-, or 2-Stop Bit Generation
Serial and Modem Control Outputs Drive a
RJ11 Cable Directly When Equipment is on the
Same Power Drop
Baud Generation (DC to 1 Mbit/s)
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False-Start Bit Detection
Complete Status Reporting Capabilities
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Capable of Running With All Existing
TL16C450 Software
3-State Output TTL Drive Capabilities for
Bidirectional Data Bus and Control Bus
After Reset, All Registers Are Identical to the
TL16C450 Register Set
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Line Break Generation and Detection
Internal Diagnostic Capabilities
Up to 48-MHz Clock Rate for up to 3-Mbps
(Standard 16× Sampling) Operation, or up to
6-Mbps (Optional 8× Sampling) Operation With
VCC = 5 V Nominal
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Loopback Controls for Communications
Link Fault Isolation
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Break, Parity, Overrun, and Framing Error
Simulation
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Up to 32-MHz Clock Rate for up to 2-Mbps
(Standard 16× Sampling) Operation, or up to
4-Mbps (Optional 8× Sampling) Operation With
VCC = 3.3 V Nominal
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Fully Prioritized Interrupt System Controls
Modem Control Functions (CTS, RTS, DSR,
DTR, RI, and DCD)
Up to 24-MHz Clock Rate for up to 1.5-Mbps
(Standard 16× Sampling) Operation, or up to
3-Mbps (Optional 8× Sampling) Operation With
VCC = 2.5 V Nominal
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Available in 44-Pin PLCC (FN) or 32-Pin QFN
(RHB) Packages
Each UART's Internal Register Set May Be
Written Concurrently to Save Setup Time
Up to 16-MHz Clock Rate for up to 1-Mbps
(Standard 16× Sampling) Operation, or up to
2-Mbps (Optional 8× Sampling) Operation With
VCC = 1.8 V Nominal
Multifunction (MF) Output Allows Users to
Select Among Several Functions, Saving
Package Pins
In TL16C450 Mode, Hold and Shift Registers
Eliminate the Need for Precise
Synchronization Between the CPU and Serial
Data
APPLICATIONS
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Point-of-Sale Terminals
Gaming Terminals
Portable Applications
Router Control
Cellular Data
Factory Automation
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Programmable Baud-Rate Generator Allows
Division of Any Input Reference Clock by 1 to
(216 – 1) and Generates an Internal 16× Clock
Standard Asynchronous Communication Bits
(Start, Stop, and Parity) Added to or Deleted
From the Serial Data Stream
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5-V, 3.3-V, 2.5-V, and 1.8-V Operation
Independent Receiver Clock Input
Transmit, Receive, Line Status, and Data Set
Interrupts Independently Controlled
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Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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