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TL16C450FNR PDF预览

TL16C450FNR

更新时间: 2024-01-16 06:49:17
品牌 Logo 应用领域
德州仪器 - TI 通信
页数 文件大小 规格书
39页 554K
描述
Single UART Without FIFO 44-PLCC 0 to 70

TL16C450FNR 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:DIP
包装说明:PLASTIC, DIP-40针数:40
Reach Compliance Code:not_compliantHTS代码:8542.31.00.01
风险等级:5.62Is Samacsys:N
地址总线宽度:3边界扫描:NO
最大时钟频率:3.072 MHz通信协议:ASYNC, BIT
数据编码/解码方法:NRZ最大数据传输速率:0.03125 MBps
外部数据总线宽度:8JESD-30 代码:R-PDIP-T40
长度:52.455 mm低功率模式:NO
DMA 通道数量:I/O 线路数量:
串行 I/O 数:1端子数量:40
片上数据RAM宽度:最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP40,.6
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
认证状态:Not QualifiedRAM(字数):0
座面最大高度:5.08 mm子类别:Serial IO/Communication Controllers
最大压摆率:10 mA最大供电电压:5.25 V
最小供电电压:4.75 V标称供电电压:5 V
表面贴装:NO技术:CMOS
温度等级:COMMERCIAL端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:15.24 mm
uPs/uCs/外围集成电路类型:SERIAL IO/COMMUNICATION CONTROLLER, SERIALBase Number Matches:1

TL16C450FNR 数据手册

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TL16C550C, TL16C550CI  
ASYNCHRONOUS COMMUNICATIONS ELEMENT  
WITH AUTOFLOW CONTROL  
SLLS177F – MARCH 1994 – REVISED MARCH 2001  
Programmable Auto-RTS and Auto-CTS  
5-V and 3.3-V Operation  
In Auto-CTS Mode, CTS Controls  
Transmitter  
Independent Receiver Clock Input  
Transmit, Receive, Line Status, and Data  
Set Interrupts Independently Controlled  
In Auto-RTS Mode, RCV FIFO Contents and  
Threshold Control RTS  
Fully Programmable Serial Interface  
Characteristics:  
– 5-, 6-, 7-, or 8-Bit Characters  
– Even-, Odd-, or No-Parity Bit Generation  
and Detection  
Serial and Modem Control Outputs Drive a  
RJ11 Cable Directly When Equipment Is on  
the Same Power Drop  
Capable of Running With All Existing  
TL16C450 Software  
– 1-, 1 1/2-, or 2-Stop Bit Generation  
– Baud Generation (dc to 1 Mbit/s)  
After Reset, All Registers Are Identical to  
the TL16C450 Register Set  
False-Start Bit Detection  
Complete Status Reporting Capabilities  
Up to 16-MHz Clock Rate for up to 1-Mbaud  
Operation  
3-State Output TTL Drive Capabilities for  
Bidirectional Data Bus and Control Bus  
In the TL16C450 Mode, Hold and Shift  
Registers Eliminate the Need for Precise  
Synchronization Between the CPU and  
Serial Data  
Line Break Generation and Detection  
Internal Diagnostic Capabilities:  
– Loopback Controls for Communications  
Link Fault Isolation  
– Break, Parity, Overrun, and Framing  
Error Simulation  
Programmable Baud Rate Generator Allows  
Division of Any Input Reference Clock by 1  
16  
to (2 1) and Generates an Internal 16×  
Clock  
Fully Prioritized Interrupt System Controls  
Standard Asynchronous Communication  
Bits (Start, Stop, and Parity) Added to or  
Deleted From the Serial Data Stream  
Modem Control Functions (CTS, RTS, DSR,  
DTR, RI, and DCD)  
description  
The TL16C550C and the TL16C550CI are functional upgrades of the TL16C550B asynchronous  
communications element (ACE), which in turn is a functional upgrade of the TL16C450. Functionally equivalent  
to the TL16C450 on power up (character or TL16C450 mode), the TL16C550C and the TL16C550CI, like the  
TL16C550B, can be placed in an alternate FIFO mode. This relieves the CPU of excessive software overhead  
by buffering received and transmitted characters. The receiver and transmitter FIFOs store up to 16 bytes  
including three additional bits of error status per byte for the receiver FIFO. In the FIFO mode, there is a  
selectable autoflow control feature that can significantly reduce software overload and increase system  
efficiency by automatically controlling serial data flow using RTS output and CTS input signals.  
The TL16C550C and TL16C550CI perform serial-to-parallel conversions on data received from a peripheral  
device or modem and parallel-to-serial conversion on data received from its CPU. The CPU can read the ACE  
status at any time. The ACE includes complete modem control capability and a processor interrupt system that  
can be tailored to minimize software management of the communications link.  
Both the TL16C550C and the TL16C550CI ACE include a programmable baud rate generator capable of  
dividing a reference clock by divisors from 1 to 65535 and producing a 16× reference clock for the internal  
transmitter logic. Provisions are included to use this 16× clock for the receiver logic. The ACE accommodates  
a 1-Mbaud serial rate (16-MHz input clock) so that a bit time is 1 µs and a typical character time is 10 µs (start  
bit, 8 data bits, stop bit).  
Two of the TL16C450 terminal functions on the TL16C550C and the TL16C550CI have been changed to  
TXRDY and RXRDY, which provide signaling to a DMA controller.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2001, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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