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TL16C550B

更新时间: 2024-11-21 22:42:11
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35页 498K
描述
ASYNCHRONOUS COMMUNICATIONS ELEMENT

TL16C550B 数据手册

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TL16C550B, TL16C550BI  
ASYNCHRONOUS COMMUNICATIONS ELEMENT  
SLLS136B – JANUARY 1994 – REVISED AUGUST 1996  
Capable of Running With All Existing  
TL16C450 Software  
Fully Programmable Serial Interface  
Characteristics:  
– 5-, 6-, 7-, or 8-Bit Characters  
– Even-, Odd-, or No-Parity Bit Generation  
and Detection  
– 1-, 1 1/2-, or 2-Stop Bit Generation  
– Baud Generation (DC to 562 Kbit/s)  
After Reset, All Registers Are Identical to  
the TL16C450 Register Set  
In the FIFO Mode, Transmitter and Receiver  
Are Each Buffered With 16-Byte FIFOs to  
Reduce the Number of Interrupts to the  
CPU  
False-Start Bit Detection  
Complete Status Reporting Capabilities  
In the TL16C450 Mode, Hold and Shift  
Registers Eliminate the Need for Precise  
Synchronization Between the CPU and  
Serial Data  
3-State Outputs Provide TTL Drive  
Capabilities for Bidirectional Data Bus and  
Control Bus  
Programmable Baud Rate Generator Allows  
Division of Any Input Reference Clock by 1  
to (2 1) and Generates an Internal 16×  
Line Break Generation and Detection  
Internal Diagnostic Capabilities:  
– Loopback Controls for Communications  
Link Fault Isolation  
16  
Clock  
Standard Asynchronous Communication  
Bits (Start, Stop, and Parity) Added to or  
Deleted From the Serial Data Stream  
– Break, Parity, Overrun, Framing Error  
Simulation  
Fully Prioritized Interrupt System Controls  
Independent Receiver Clock Input  
Modem Control Functions (CTS, RTS, DSR,  
DTR, RI, and DCD)  
Transmit, Receive, Line Status, and Data  
Set Interrupts Independently Controlled  
Faster Plug-In Replacement for National  
Semiconductor NS16550A  
description  
The TL16C550B and the TL16C550BI are functional upgrades of the TL16C450 asynchronous  
communications element (ACE). Functionally identical to the TL16C450 on power up (character mode ), the  
TL16C550B and TL16C550BI can be placed in an alternate mode (FIFO) to relieve the CPU of excessive  
software overhead.  
In this alternate FIFO mode, internal FIFOs are activated allowing 16 bytes (plus 3 bits of error data per byte  
in the receiver FIFO) to be stored in both receive and transmit modes. To minimize system overhead and  
maximize system efficiency, all logic is on the chip. Two of the TL16C450 terminal functions (RXRDY and  
TXRDY) have been changed to allow signalling of DMA transfers.  
The TL16C550B and the TL16C550BI perform serial-to-parallel conversions on data received from a peripheral  
device or modem and parallel-to-serial conversion on data received from its CPU. The CPU can read and report  
on the status of the ACE at any point in the ACE operation. Reported status information includes: the type of  
transfer operation in progress, the status of the operation, and any error conditions encountered.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
The TL16C550B and the TL16C550BI can also be reset to the TL16C450 mode under software control.  
Copyright 1996, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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