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TL16C550CIFNR PDF预览

TL16C550CIFNR

更新时间： 2024-11-22 12:01:35
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德州仪器 - TI 通信
页数 文件大小 规格书
43页 1020K
描述
ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH AUTOFLOW CONTROL

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TL16C550CIFNR 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：LCC
包装说明：QCCJ, LDCC44,.7SQ针数：44
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：1.68
地址总线宽度：3边界扫描：NO
最大时钟频率：16 MHz通信协议：ASYNC, BIT
数据编码/解码方法：NRZ最大数据传输速率：0.125 MBps
外部数据总线宽度：8JESD-30 代码：S-PQCC-J44
JESD-609代码：e4长度：16.59 mm
低功率模式：NO湿度敏感等级：3
串行 I/O 数：1端子数量：44
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：QCCJ
封装等效代码：LDCC44,.7SQ封装形状：SQUARE
封装形式：CHIP CARRIER峰值回流温度（摄氏度）：260
电源：3.3/5 V认证状态：Not Qualified
座面最大高度：4.57 mm子类别：Serial IO/Communication Controllers
最大压摆率：10 mA最大供电电压：5.25 V
最小供电电压：4.75 V标称供电电压：5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：J BEND端子节距：1.27 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：16.59 mmuPs/uCs/外围集成电路类型：SERIAL IO/COMMUNICATION CONTROLLER, SERIAL
Base Number Matches：1

TL16C550CIFNR 数据手册

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SLLS177H − MARCH 1994 − REVISED JANUARY 2006  
D
D
D
D
Programmable Auto-RTS and Auto-CTS  
D
D
D
D
5-V and 3.3-V Operation  
In Auto-CTS Mode, CTS Controls  
Transmitter  
Independent Receiver Clock Input  
Transmit, Receive, Line Status, and Data  
Set Interrupts Independently Controlled  
In Auto-RTS Mode, RCV FIFO Contents and  
Threshold Control RTS  
Fully Programmable Serial Interface  
Characteristics:  
− 5-, 6-, 7-, or 8-Bit Characters  
− Even-, Odd-, or No-Parity Bit Generation  
and Detection  
Serial and Modem Control Outputs Drive a  
RJ11 Cable Directly When Equipment Is on  
the Same Power Drop  
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Capable of Running With All Existing  
TL16C450 Software  
− 1-, 1 1/2-, or 2-Stop Bit Generation  
− Baud Generation (dc to 1 Mbit/s)  
After Reset, All Registers Are Identical to  
the TL16C450 Register Set  
D
D
D
False-Start Bit Detection  
Complete Status Reporting Capabilities  
Up to 16-MHz Clock Rate for up to 1-Mbaud  
Operation  
3-State Output TTL Drive Capabilities for  
Bidirectional Data Bus and Control Bus  
In the TL16C450 Mode, Hold and Shift  
Registers Eliminate the Need for Precise  
Synchronization Between the CPU and  
Serial Data  
D
Line Break Generation and Detection  
D
Internal Diagnostic Capabilities:  
− Loopback Controls for Communications  
Link Fault Isolation  
− Break, Parity, Overrun, and Framing  
Error Simulation  
D
D
Programmable Baud Rate Generator Allows  
Division of Any Input Reference Clock by 1  
16  
to (2 −1) and Generates an Internal 16×  
Clock  
D
D
Fully Prioritized Interrupt System Controls  
Standard Asynchronous Communication  
Bits (Start, Stop, and Parity) Added to or  
Deleted From the Serial Data Stream  
Modem Control Functions (CTS, RTS, DSR,  
DTR, RI, and DCD)  
description  
The TL16C550C and the TL16C550CI are functional upgrades of the TL16C550B asynchronous  
communications element (ACE), which in turn is a functional upgrade of the TL16C450. Functionally equivalent  
to the TL16C450 on power up (character or TL16C450 mode), the TL16C550C and the TL16C550CI, like the  
TL16C550B, can be placed in an alternate FIFO mode. This relieves the CPU of excessive software overhead  
by buffering received and transmitted characters. The receiver and transmitter FIFOs store up to 16 bytes  
including three additional bits of error status per byte for the receiver FIFO. In the FIFO mode, there is a  
selectable autoflow control feature that can significantly reduce software overload and increase system  
efficiency by automatically controlling serial data flow using RTS output and CTS input signals.  
The TL16C550C and TL16C550CI perform serial-to-parallel conversions on data received from a peripheral  
device or modem and parallel-to-serial conversion on data received from its CPU. The CPU can read the ACE  
status at any time. The ACE includes complete modem control capability and a processor interrupt system that  
can be tailored to minimize software management of the communications link.  
Both the TL16C550C and the TL16C550CI ACE include a programmable baud rate generator capable of  
dividing a reference clock by divisors from 1 to 65535 and producing a 16× reference clock for the internal  
transmitter logic. Provisions are included to use this 16× clock for the receiver logic. The ACE accommodates  
a 1-Mbaud serial rate (16-MHz input clock) so that a bit time is 1 µs and a typical character time is 10 µs (start  
bit, 8 data bits, stop bit).  
Two of the TL16C450 terminal functions on the TL16C550C and the TL16C550CI have been changed to  
TXRDY and RXRDY, which provide signaling to a DMA controller.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
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Copyright 1994 − 2006, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...43

中文翻译

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TL16C550CIFNR 替代型号

型号 品牌 替代类型 描述 数据表
TL16C550CIFN TI

完全替代

 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH AUTOFLOW CONTROL
TL16C550CFN TI

类似代替

 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH AUTOFLOW CONTROL
TL16C450FN TI

类似代替

 ASYNCHRONOUS COMMUNICATIONS ELEMENT

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