TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057D – AUGUST 1989 – REVISED MARCH 1996
Capable of Running With All Existing
TL16C450 Software
Fully Programmable Serial Interface
Characteristics:
– 5-, 6-, 7-, or 8-Bit Characters
– Even-, Odd-, or No-Parity Bit Generation
and Detection
– 1-, 1 1/2-, or 2-Stop Bit Generation
– Baud Generation (dc to 256 Kbit/s)
After Reset, All Registers Are Identical to
the TL16C450 Register Set
In the FIFO Mode, Transmitter and Receiver
Are Each Buffered With 16-Byte FIFOs to
Reduce the Number of Interrupts to the
CPU
False-Start Bit Detection
Complete Status Reporting Capabilities
In the TL16C450 Mode, Holding and Shift
Registers Eliminate the Need for Precise
Synchronization Between the CPU and
Serial Data
3-State TTL Drive Capabilities for
Bidirectional Data Bus and Control Bus
Line Break Generation and Detection
Programmable Baud Rate Generator Allows
Division of Any Input Reference Clock by 1
to (2 –1) and Generates an Internal 16×
Internal Diagnostic Capabilities:
– Loopback Controls for Communications
Link Fault Isolation
– Break, Parity, Overrun, Framing Error
Simulation
16
Clock
Standard Asynchronous Communication
Bits (Start, Stop, and Parity) Added to or
Deleted From the Serial Data Stream
Fully Prioritized Interrupt System Controls
Modem Control Functions (CTS, RTS, DSR,
DTR, RI, and DCD)
Independent Receiver Clock Input
Transmit, Receive, Line Status, and Data
Set Interrupts Independently Controlled
Faster Plug-In Replacement for National
Semiconductor NS16550A
description
The TL16C550A is a functional upgrade of the TL16C450 asynchronous communications element (ACE).
†
Functionally identical to the TL16C450 on power up (character mode ), the TL16C550A can be placed in an
alternate mode (FIFO) to relieve the CPU of excessive software overhead.
In this mode, internal FIFOs are activated allowing 16 bytes (plus 3 bits of error data per byte in the receiver
FIFO) to be stored in both receive and transmit modes. To minimize system overhead and maximize system
efficiency, all logic is on the chip. Two of the TL16C450 terminal functions (terminals 24 and 29 on the N package
and terminals 27 and 32 on the FN package) have been changed to allow signalling of direct memory address
(DMA) transfers.
The TL16C550A performs serial-to-parallel conversion on data received from a peripheral device or modem
and parallel-to-serial conversion on data received from its CPU. The CPU can read and report on the status of
the ACE at any point in the ACE’s operation. Reported status information includes the type of transfer operation
in progress, the status of the operation, and any error conditions encountered.
The TL16C550A ACE includes a programmable, on-board, baud rate generator. This generator is capable of
16
dividing a reference clock input by divisors from 1 to (2 –1) and producing a 16× clock for driving the internal
transmitter logic. Provisions are included to use this 16× clock to drive the receiver logic. Also included in the
ACE is a complete modem control capability and a processor interrupt system that may be software tailored
to the user’s requirements to minimize the computing required to handle the communications link.
†
The TL16C550A can also be reset to the TL16C450 mode under software control.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
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