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TC55VZM216AJJN-10 PDF预览

TC55VZM216AJJN-10

更新时间: 2024-11-08 08:53:23
品牌 Logo 应用领域
东芝 - TOSHIBA /
页数 文件大小 规格书
11页 186K
描述
262,144-WORD BY 16-BIT CMOS STATIC RAM

TC55VZM216AJJN-10 数据手册

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TC55VZM216AJJN/AFTN08,10,12  
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS  
262,144-WORD BY 16-BIT CMOS STATIC RAM  
DESCRIPTION  
The TC55VZM216AJJN/AFTN is a 4,194,304-bit high-speed static random access memory (SRAM) organized as  
262,144 words by 16 bits. Fabricated using CMOS technology and advanced circuit techniques to provide high  
speed, it operates from a single 3.3 V power supply. Chip enable (CE ) can be used to place the device in a  
low-power mode, and output enable ( OE ) provides fast memory access. Data byte control signals ( LB , UB ) provide  
lower and upper byte access. This device is well suited to cache memory applications where high-speed access and  
high-speed storage are required. All inputs and outputs are directly LVTTL compatible. The  
TC55VZM216AJJN/AFTN is available in plastic 44-pin SOJ and TSOP with 400mil width for high density surface  
assembly.  
FEATURES  
Single power supply voltage of 3.3 V 0.3 V  
Fully static operation  
Fast access time (the following are maximum values)  
TC55VZM216AJJN/AFTN08:8 ns  
All inputs and outputs are LVTTL compatible  
Output buffer control using OE  
Data byte control using LB (I/O1 to I/O8) and  
UB (I/O9 to I/O16)  
TC55VZM216AJJN/AFTN10:10 ns  
TC55VZM216AJJN/AFTN12:12 ns  
Low-power dissipation (IDDO2  
)
(the following are maximum values)  
Package:  
Cycle Time  
8
10  
12  
ns  
SOJ44-P-400-1.27 (AJJN)  
(Weight: 1.64 g typ)  
TSOP II44-P-400-0.80 (AFTN) (Weight: 0.45 g typ)  
Operation (max) 140  
130  
120  
mA  
Standby:4 mA (both devices)  
PIN ASSIGNMENT (TOP VIEW)  
44 PIN SOJ 44 PIN TSOP  
PIN NAMES  
A0 to A17  
Address Inputs  
A4  
1
2
3
4
5
6
7
8
9
44 A5  
43 A6  
42 A7  
A4  
A3  
A2  
A1  
A0  
1
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
A5  
A6  
A7  
OE  
UB  
LB  
I/O1 to I/O16 Data Inputs/Outputs  
A3  
A2  
A1  
A0  
2
3
CE  
WE  
Chip Enable Input  
Write Enable Input  
Output Enable Input  
Data Byte Control Inputs  
Power (+3.3 V)  
41  
40  
39  
4
OE  
UB  
LB  
5
6
CE  
CE  
I/O1  
38 I/O16  
37 I/O15  
36 I/O14  
35 I/O13  
34 GND  
33 VDD  
I/O1  
7
I/O16  
I/O15  
I/O14  
I/O13  
GND  
VDD  
OE  
I/O2  
I/O3  
I/O2  
I/O3  
I/O4  
VDD  
8
9
I/O4 10  
VDD 11  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
LB , UB  
GND 12  
I/O5 13  
I/O6 14  
I/O7 15  
I/O8 16  
GND  
I/O5  
I/O6  
I/O7  
I/O8  
WE  
A15  
A14  
A13  
A12  
A16  
V
DD  
32 I/O12  
31 I/O11  
30 I/O10  
29 I/O9  
28 NU  
27 A8  
26 A9  
25 A10  
24 A11  
23 A17  
I/O12  
I/O11  
I/O10  
I/O9  
NU  
GND  
NU  
Ground  
Not Usable (Input)  
17  
WE  
A15 18  
A14 19  
A13 20  
A12 21  
A16 22  
A8  
A9  
A10  
A11  
A17  
(TC55VZM216AFTN)  
(TC55VZM216AJJN)  
2003-01-17 1/11  

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