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SY100ELT28ZCTR PDF预览

SY100ELT28ZCTR

更新时间: 2024-09-13 08:56:59
品牌 Logo 应用领域
麦瑞 - MICREL 转换器电平转换器驱动程序和接口锁存器接口集成电路光电二极管
页数 文件大小 规格书
7页 87K
描述
5V TTL-TO-DIFFERENTIAL PECL AND DIFFERENTIAL PECL-TO-TTL TRANSLATOR

SY100ELT28ZCTR 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:SOP, SOP8,.25Reach Compliance Code:compliant
风险等级:5.69Is Samacsys:N
最大延迟:5.5 ns接口集成电路类型:PECL-TTL/TTL-PECL TRANSLATOR
JESD-30 代码:R-PDSO-G8JESD-609代码:e0
长度:4.93 mm湿度敏感等级:1
位数:1功能数量:1
端子数量:8最高工作温度:85 °C
最低工作温度:-40 °C输出锁存器或寄存器:NONE
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP8,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):240电源:5 V
认证状态:Not Qualified座面最大高度:1.73 mm
子类别:Other Interface ICs最大供电电压:5.5 V
最小供电电压:4.5 V标称供电电压:5 V
表面贴装:YES技术:ECL100K
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:3.95 mmBase Number Matches:1

SY100ELT28ZCTR 数据手册

 浏览型号SY100ELT28ZCTR的Datasheet PDF文件第2页浏览型号SY100ELT28ZCTR的Datasheet PDF文件第3页浏览型号SY100ELT28ZCTR的Datasheet PDF文件第4页浏览型号SY100ELT28ZCTR的Datasheet PDF文件第5页浏览型号SY100ELT28ZCTR的Datasheet PDF文件第6页浏览型号SY100ELT28ZCTR的Datasheet PDF文件第7页 
5V TTL-TO-DIFFERENTIAL PECL  
AND DIFFERENTIAL PECL-TO-TTL  
TRANSLATOR  
SY10ELT28  
SY100ELT28  
FINAL  
FEATURES  
DESCRIPTION  
Guaranteed AC parameters over temperature:  
The SY10/100ELT28 is a differential PECL-to-TTL  
translator and a TTL-to-differential PECL translator in a  
single package. Because PECL (Positive ECL) levels are  
used, only +5V and ground are required. The small outline  
8-pin package and the dual translation design of the  
ELT28 makes it ideal for applications which are sending  
and receiving signals across a backplane.  
• fMAX > 160MHz (TTL)  
• < 5.5ns PECL-to-TTL propagation delay  
• < 1.5ns tr / tf; PECL output  
• < 1.3ns TTL-to-PECL propagation delay  
Wide temperature range: –40°C to +85°C  
5V power supply  
Q  
output will default low with inputs left open  
TTL  
or < 1.3V  
Q  
output will default high with inputs left open  
ECL  
Internal PECL input pulldown resistors  
Available in 8-pin MSOP and SOIC packages  
PIN NAMES  
PIN CONFIGURATION/BLOCK DIAGRAM  
Pin  
DTTL  
Function  
TTL Inputs  
DECL  
/DECL  
QECL  
/QECL  
1
2
3
4
8
7
6
5
VCC  
QTTL  
TTL Outputs  
QTTL  
DTTL  
GND  
PECL  
TTL  
DECL, /DECL  
QECL, /QECL  
VCC  
PECL Differential Inputs  
PECL Differential Outputs  
Positive Supply  
GND  
Ground  
TOP VIEW  
(Available in MSOP or SOIC package)  
Rev.: B  
Amendment:/0  
Issue Date: February 2003  
1

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