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SY100EL29VZCTR PDF预览

SY100EL29VZCTR

更新时间: 2024-11-04 22:07:39
品牌 Logo 应用领域
麦瑞 - MICREL 触发器逻辑集成电路光电二极管时钟
页数 文件大小 规格书
4页 68K
描述
5V/3.3V DUAL DIFFERENTIAL DATA AND CLOCK D FLIP-FLOP w/SET AND RESET

SY100EL29VZCTR 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:0.300 INCH, SOIC-20
针数:20Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.2
其他特性:WITH DIFFERENTIAL CLOCK系列:100EL
JESD-30 代码:R-PDSO-G20JESD-609代码:e0
长度:12.8 mm逻辑集成电路类型:D FLIP-FLOP
湿度敏感等级:1位数:1
功能数量:2端子数量:20
最高工作温度:85 °C最低工作温度:
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP20,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):240
电源:-4.5 V最大电源电流(ICC):50 mA
传播延迟(tpd):0.7 ns认证状态:Not Qualified
座面最大高度:2.65 mm子类别:FF/Latches
表面贴装:YES技术:ECL
温度等级:COMMERCIAL EXTENDED端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
触发器类型:POSITIVE EDGE宽度:7.5 mm
最小 fmax:1100 MHzBase Number Matches:1

SY100EL29VZCTR 数据手册

 浏览型号SY100EL29VZCTR的Datasheet PDF文件第2页浏览型号SY100EL29VZCTR的Datasheet PDF文件第3页浏览型号SY100EL29VZCTR的Datasheet PDF文件第4页 
5V/3.3V DUAL DIFFERENTIAL  
DATA AND CLOCK  
D FLIP-FLOP w/SET AND RESET  
ClockWorks™  
SY100EL29V  
DESCRIPTION  
FEATURES  
3.3V and 5V power supply option  
Differential D, CLK and Q  
The SY100EL29V is a dual differential register with  
differential data (inputs and outputs) and clock. The  
registers are triggered by a positive transition of the  
positive clock (CLK) input. A HIGH on the Reset (Rx)  
asynchronously resets the appropriate register so that  
the Q outputs go LOW. A HIGH on the Set (Sx)  
asynchronously resets the appropriate register so that  
the Q outputs go HIGH. The Set and Reset inputs cannot  
both be HIGH simultaneously.  
The differential input structures are clamped so that  
the inputs of unused registers can be left open without  
upsetting the bias network of the devices. The clamping  
action will assert the /D and the /CLK sides of the inputs.  
Extended V range of –3.0V to –5.5V  
EE  
V output for single-ended use  
BB  
1100MHz min. toggle frequency  
Asynchronous Reset and Set  
Fully compatible with Motorola MC100LVEL29 and  
MC100EL29  
Available in 20-pin SOIC package  
The noninverting input will pull down to V and the  
EE  
PIN CONFIGURATION/BLOCK DIAGRAM  
inverting input will be biased around V /2. Because of  
CC  
the edge-triggered flip-flop nature of the devices,  
simultaneously opening both the clock and data inputs  
will result in an output which reaches an unidentified but  
valid state.  
R0 VCC Q0  
S0 S1 VCC Q1 Q1 VEE  
Q0  
20 19 18 17 16 15 14 13 12 11  
The fully differential design of the devices makes them  
ideal for very high frequency applications where a  
registered data path is necessary.  
Q
Q
Q
Q
R
S
R
S
D
CLK  
D
CLK  
1
2
3
4
5
6
7
8
9
10  
D0 D0 CLK0CLK0 VBB D1 D1 CLK1CLK1 R1  
SOIC  
TOP VIEW  
PIN NAMES  
TRUTH TABLE  
Pin  
CLK, /CLK  
D[0:1], /D[0:1]  
Q[0:1], /Q[0:1]  
R0, R1  
Function  
Differential Clock Inputs  
Differential Data Inputs  
Differential Data Outputs  
Reset Inputs  
R
S
L
D
L
CLK  
Z
Q
/Q  
L
L
H
H
L
L
H
X
X
X
Z
L
H
H
L
L
X
L
H
H
X
H
L
S0, S1  
Set Inputs  
H
X
Undef  
Undef  
VBB  
VBB Reference Output  
VCC  
NOTE:  
Z = LOW-to-HIGH Transition  
VCC  
VEE  
VEE  
Rev.: B  
Amendment:/0  
Issue Date: February 2000  
1

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