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STLC1510 PDF预览

STLC1510

更新时间: 2024-11-23 21:54:03
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS /
页数 文件大小 规格书
40页 426K
描述
NorthenLite G.lite DMT Transceiver

STLC1510 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:BGA包装说明:12 X 12 MM, 1.70 MM HEIGHT, LFBGA-132
针数:132Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.84
数据速率:1500 MbpsJESD-30 代码:S-PBGA-B132
JESD-609代码:e3长度:12 mm
湿度敏感等级:1功能数量:1
端子数量:132最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:LFBGA封装等效代码:BGA132,14X14,32
封装形状:SQUARE封装形式:GRID ARRAY, LOW PROFILE, FINE PITCH
峰值回流温度(摄氏度):225电源:2.5,3.3 V
认证状态:Not Qualified座面最大高度:1.7 mm
子类别:Other Telecom ICs标称供电电压:2.5 V
表面贴装:YES电信集成电路类型:MODEM
温度等级:INDUSTRIAL端子面层:MATTE TIN
端子形式:BALL端子节距:0.8 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:12 mmBase Number Matches:1

STLC1510 数据手册

 浏览型号STLC1510的Datasheet PDF文件第2页浏览型号STLC1510的Datasheet PDF文件第3页浏览型号STLC1510的Datasheet PDF文件第4页浏览型号STLC1510的Datasheet PDF文件第5页浏览型号STLC1510的Datasheet PDF文件第6页浏览型号STLC1510的Datasheet PDF文件第7页 
STLC1510  
NorthenLite G.lite DMT Transceiver  
PRODUCT PREVIEW  
ATM transport  
Forward Error correction & interleaving  
Framing & de-framing  
DMT modulation and demodulation  
Start-up & showtime control processing  
LBGA132  
ORDERING NUMBER: STLC1510  
In addition, the STLC1510 provides the following fea-  
tures:  
Serial and Parallel network interface at back-  
end to CO equipment  
1.0 GENERAL DESCRIPTION  
Serial interface to the AFE chip STLC1511  
The STLC1510 is a high-speed modem chip that pro-  
vides the digital portion of a G.992.2 DSL access at a  
Central Office (CO) site. It provides downstream and  
upstream data transport between an ATM byte  
stream and an analog front-end chip using Discrete  
Multi-Tone (DMT) Modulation.  
Access to off chip memory  
Power-up boot program stored in ROM  
132 balls 12x12x1.7 mm LBGA package  
Power Consumption: 0.75 Watt  
Power Supp.: 2.5 V (core) and 3.3 V (I/O ring)  
The STLC1510 is compliant with ITU-T G.992.2  
(G.Lite), G.996.1 (G.Test), G.994.1 (G.Handshake),  
G.997.1 (G.Ploam).  
Figure 1. Block Diagram  
8
3
TxClk  
TxClav  
TxEnb  
TxSOC  
HPI  
DFE  
UTxData[7:0]  
TxAddr[4:0]  
TxParity  
TxBP  
EPM  
BPU  
NIF  
TxSOUT[1:0]  
FEC  
MAP  
A_SCLK  
CK35M  
RxClk  
RxClav  
RxEnb  
RxSOC  
ARM  
D950  
Dual  
MAC  
RxSIN[1:0]  
URxData[7:0]  
RxAddr[4:0]  
RxParity  
LAMBA Bus  
REF_CLK  
7
VDD3_3  
TGB  
TAP  
SPI_CLK  
SPI_ENB  
7
VDD2_5  
VSS  
14  
2
2
8
SPI_DTX  
SPI_DRX  
November 2000  
1/40  
This is preliminary information on a new product now in development. Details are subject to change without notice.  

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