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STLC2500ATR PDF预览

STLC2500ATR

更新时间: 2024-11-27 03:30:51
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 蓝牙
页数 文件大小 规格书
37页 339K
描述
Bluetooth Single Chip

STLC2500ATR 数据手册

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STLC2500A  
BluetoothTM Single Chip  
Preliminary Data  
Features  
Lowest power consumption  
Efficient support for WLAN coexistence in  
collocated scenario  
Auto calibration (VCO, Filters)  
Standard TFBGA 84 pins package  
– No need for calibration of the RF part  
Ciphering support up to 128 bits key  
Total number of external components limited to  
Software support up to HCI stack  
7 (6 decoupling capacitors and 1 filter)  
– H4 HCI Transport Layer  
Bluetooth™ specification compliance: V1.1  
– HCI proprietary commands and single HCI  
command for patch/upgrade download  
and V1.2  
Ericsson Technology Licensing Baseband  
Single power supply with internal regulators  
Supports 1.65 to 2.85 Volts IO systems  
Timer and watchdog  
Core (EBC)  
Point-to-point, point-to-multi-point (up to 7  
slaves) and scatternet capability  
Power class 2. Power class 1 compatible  
(with external power amplifier)  
Asynchronous Connection Oriented (ACL)  
logical transport link  
Ultra low power architecture with 3 different low  
power modes: sleep , deep sleep, complete  
power down  
Synchronous Connection Oriented (SCO) link:  
2 simultaneous SCO channels  
Supports Pitch-Period Error Concealment  
Dual Wake-up mechanism: initiated by the  
(PPEC)  
Host or by the Bluetooth device  
Adaptive Frequency Hopping (AFH): hopping  
kernel, channel assessment (master & slave)  
Description  
Faster connection: Interlaced scan for Page  
and Inquiry scan, first FHS without random  
back off, RSSI used to limit range  
The STLC2500A is a single chip ROM-based  
Bluetooth solution implemented in 0.13 µm ultra  
low power, low leakage CMOS technology for  
mobile terminal applications requiring integration  
up to HCI level. Patch RAM is available, enabling  
multiple patches/upgrades. The STLC2500A  
offers multiple interface options. The radio has  
been designed for single chip requirements and  
minimal power consumption.  
Extended SCO (eSCO) links  
HW support for ACL, SCO and eSCO packet  
types (see Overview)  
Clock support for all cellular standards: system  
clock input and low power clock  
ARM7TDMI CPU with 32-bit core and AMBA  
(AHB-APB) bus configuration  
Order codes  
Patch RAM capability  
Part number  
Package  
TFBGA84  
TFBGA84  
Packing  
Tray  
Tape on Reel  
Memory organization: on-chip RAM & ROM  
Communication interfaces: UART, PCM and  
STLC2500A  
I2C interfaces and 4 programmable GPIOs  
STLC2500ATR  
February 2006  
Rev1  
1/37  
www.st.com  
37  

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