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STLC2500C PDF预览

STLC2500C

更新时间: 2024-11-27 03:30:51
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页数 文件大小 规格书
4页 40K
描述
BluetoothTM EDR Single Chip

STLC2500C 数据手册

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STLC2500C  
BluetoothTM EDR Single Chip  
DATA BRIEF  
Features  
The lowest power consumption by design and  
technology (see Table 1)  
WFBGA48 (4.5mm x 4.5 mmx 0.8 mm)  
On-chip RAM, on-chip ROM  
World best EDR throughput (see Table 1)  
World most performing BT-WLAN coexistence  
support for several BT/WLAN coexistence  
algorithms (i.e. 2/3/4-wire PTA, in a very  
flexible and parametrical way to optimize voice  
and data quality over Bluetooth and WLAN)  
Communication interfaces  
– Fast UART up to 4Mbps for HCI  
– SPI interface up to 6 Mbps for HCI  
– PCM interface for voice  
Superior voice quality  
– WirelessLAN coexistence with 2, 3, 4 wires  
– 19 programmable GPIOs  
– Pitch-Period Error Concealment (PPEC) for  
improved speech quality (in the vicinity of  
interference)  
– Fast master I2C interface  
Extended range  
Ciphering support up to 128-bit keys  
– Tx output power up to 8 dBm  
Software support up to HCI stack  
Pre-calibrated RF  
– H4 and H5 HCI transport layer  
– Auto calibration (VCO, filters), no RF  
calibration required in production  
– HCI proprietary commands and single HCI  
command for patch/upgrade download  
Bluetooth™V2.0 + EDR compliant  
– Full EDR support and all BT1.2 errata  
– All EDR data rates and packet types  
Internal power management  
Supports 1.65V to 2.85 Volts IO systems  
Seven external components: six decoupling  
Backward compatibility with legacy devices  
capacitors and one single antenna interface  
through extended V1.2 feature support  
Ultra low power architecture with 3 different low  
power modes: sleep , deep sleep and  
complete power down  
– Adaptive Frequency Hopping (AFH)  
– Faster connections through interlaced scan  
– Extended SCO (eSCO) links  
Description  
Point-to-point, point-to-multi-point  
(up to 7 slaves) and scatternet capability  
The STLC2500C is a single chip ROM-based  
Bluetooth solution implemented in 0.13 µm ultra  
low power, ultra low leakage CMOS technology  
for mobile terminal applications requiring  
integration up to HCI level. Patch RAM is  
available, enabling multiple patches/upgrades.  
The STLC2500C offers multiple interface options.  
The radio has been designed specifically for  
single chip requirements for minimal consumption  
and BOM count.  
Asynchronous Connection-Less (ACL) logical  
transport link  
Synchronous Connection Oriented (SCO) link  
for 2 simultaneous SCO channels at 64Kbps  
Clock support for all cellular standards: system  
clock input and low power clock  
ARM7TDMI CPU with 32-bit core and AMBA  
(AHB-APB) bus configuration  
Patch RAM capability  
January 2006  
Rev 1  
1/4  
For further information contact your local STMicroelectronics sales office.  
www.st.com  
4

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